(globals
version = 3
io_order = default
)
(iopin
(top
(pin name="PCLK" offset=0.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PCLKG" offset=3.5900 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRESETn" offset=6.8800 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PSEL" offset=10.1650 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[11]" offset=13.4500 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[10]" offset=16.7350 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[9]" offset=20.0200 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[8]" offset=23.3050 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[7]" offset=26.5900 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[6]" offset=29.8750 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[5]" offset=33.1600 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[4]" offset=36.4450 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[3]" offset=39.7300 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PADDR[2]" offset=43.0150 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PENABLE" offset=46.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWRITE" offset=49.5850 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[31]" offset=52.8700 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[30]" offset=56.1550 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[29]" offset=59.4400 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[28]" offset=62.7250 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[27]" offset=66.0100 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[26]" offset=69.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
)
(left
(pin name="PWDATA[25]" offset=0.2000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[24]" offset=3.0250 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[23]" offset=5.8500 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[22]" offset=8.6750 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[21]" offset=11.5000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[20]" offset=14.3200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[19]" offset=17.1400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[18]" offset=19.9600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[17]" offset=22.7800 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[16]" offset=25.6000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[15]" offset=28.4200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[14]" offset=31.2400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[13]" offset=34.0600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[12]" offset=36.8800 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[11]" offset=39.7000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[10]" offset=42.5200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[9]" offset=45.3400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[8]" offset=48.1600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[7]" offset=50.9850 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[6]" offset=53.8100 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[5]" offset=56.6350 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[4]" offset=59.4600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
)
(bottom
(pin name="PWDATA[3]" offset=0.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[2]" offset=3.5900 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[1]" offset=6.8800 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PWDATA[0]" offset=10.1650 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="ECOREVNUM[3]" offset=13.4500 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="ECOREVNUM[2]" offset=16.7350 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="ECOREVNUM[1]" offset=20.0200 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="ECOREVNUM[0]" offset=23.3050 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[31]" offset=26.5900 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[30]" offset=29.8750 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[29]" offset=33.1600 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[28]" offset=36.4450 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[27]" offset=39.7300 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[26]" offset=43.0150 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[25]" offset=46.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[24]" offset=49.5850 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[23]" offset=52.8700 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[22]" offset=56.1550 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[21]" offset=59.4400 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[20]" offset=62.7250 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[19]" offset=66.0100 layer=2 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[18]" offset=69.3000 layer=2 width=0.0700 depth=0.2900 place_status=placed )
)
(right
(pin name="PRDATA[17]" offset=0.2000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[16]" offset=3.0250 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[15]" offset=5.8500 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[14]" offset=8.6750 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[13]" offset=11.5000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[12]" offset=14.3200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[11]" offset=17.1400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[10]" offset=19.9600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[9]" offset=22.7800 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[8]" offset=25.6000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[7]" offset=28.4200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[6]" offset=31.2400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[5]" offset=34.0600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[4]" offset=36.8800 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[3]" offset=39.7000 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[2]" offset=42.5200 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[1]" offset=45.3400 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PRDATA[0]" offset=48.1600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PREADY" offset=50.9850 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="PSLVERR" offset=53.8100 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="EXTIN" offset=56.6350 layer=3 width=0.0700 depth=0.2900 place_status=placed )
(pin name="TIMERINT" offset=59.4600 layer=3 width=0.0700 depth=0.2900 place_status=placed )
)
)
TMSY Tutorials
apb_timer.pins.io
import design = innovus -stylus
set_db write_def_hierarchy_delimiter /
set_db init_netlist_files ../logical_synthesis/outputs_Mar14-02:18:47/apb_timer_m.v
set_db init_lef_files ../logical_synthesis/lib_search_path/gsclib045.fixed2.lef
set_db init_power_nets VDD
set_db init_ground_nets VSS
set_db init_mmmc_files ../mmmc/apb_timer.view
set_db init_power_nets VDD
set_db init_power_nets VDD
set_db init_ground_nets VSS
set_db init_ground_nets VSS
read_mmmc ../mmmc/apb_timer.view
read_physical -lef ../logical_synthesis/lib_search_path/gsclib045.fixed2.lef
read_netlist ../logical_synthesis/outputs_Mar14-02:18:47/apb_timer_m.v
set_current_design {}
init_design
eval_legacy { setLibraryUnit -time none -internal }
set_db floorplan_is_max_io_height 1
set_io_flow_flag 0
create_floorplan -core_density_size 1.0 0.7 0 0 0 0 -flip f
report_resource
report_resource -start {Constraint file reading stats}
get_ports PCLK
report_resource -end {Constraint file reading stats}
report_resource
=============================================================================
create_floorplan -site CoreSite -core_density_size 0.945815835297 0.499997 4 4 4 4
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 1 -spread_type center -spacing 0.19 -pin {PCLK PCLKG PRESETn PSEL {PADDR[2]} {PADDR[3]} {PADDR[4]} {PADDR[5]} {PADDR[6]} {PADDR[7]} {PADDR[8]} {PADDR[9]} {PADDR[10]} {PADDR[11]} PENABLE {ECOREVNUM[0]} {ECOREVNUM[1]} {ECOREVNUM[2]} {ECOREVNUM[3]} EXTIN}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.06 -pin_depth 0.335 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 1 -spread_type center -spacing 0.19 -pin {PCLK PCLKG PRESETn PSEL {PADDR[2]} {PADDR[3]} {PADDR[4]} {PADDR[5]} {PADDR[6]} {PADDR[7]} {PADDR[8]} {PADDR[9]} {PADDR[10]} {PADDR[11]} PENABLE {ECOREVNUM[0]} {ECOREVNUM[1]} {ECOREVNUM[2]} {ECOREVNUM[3]} EXTIN}
set_db assign_pins_edit_in_batch 0
gui_fit
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 2 -spread_type center -spacing 0.19 -pin {{PWDATA[0]} {PWDATA[1]} {PWDATA[2]} {PWDATA[3]} {PWDATA[4]} {PWDATA[5]} {PWDATA[6]} {PWDATA[7]} {PWDATA[8]} {PWDATA[9]} {PWDATA[10]} {PWDATA[11]} {PWDATA[12]} {PWDATA[13]} {PWDATA[14]} {PWDATA[15]} {PWDATA[16]} {PWDATA[17]} {PWDATA[18]} {PWDATA[19]} {PWDATA[20]} {PWDATA[21]} {PWDATA[22]} {PWDATA[23]} {PWDATA[24]} {PWDATA[25]} {PWDATA[26]} {PWDATA[27]} {PWDATA[28]} {PWDATA[29]} {PWDATA[30]} {PWDATA[31]}}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.07 -pin_depth 0.29 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 2 -spread_type center -spacing -0.2 -pin {{PWDATA[0]} {PWDATA[1]} {PWDATA[2]} {PWDATA[3]} {PWDATA[4]} {PWDATA[5]} {PWDATA[6]} {PWDATA[7]} {PWDATA[8]} {PWDATA[9]} {PWDATA[10]} {PWDATA[11]} {PWDATA[12]} {PWDATA[13]} {PWDATA[14]} {PWDATA[15]} {PWDATA[16]} {PWDATA[17]} {PWDATA[18]} {PWDATA[19]} {PWDATA[20]} {PWDATA[21]} {PWDATA[22]} {PWDATA[23]} {PWDATA[24]} {PWDATA[25]} {PWDATA[26]} {PWDATA[27]} {PWDATA[28]} {PWDATA[29]} {PWDATA[30]} {PWDATA[31]}}
set_db assign_pins_edit_in_batch 0
=============================================================================
get_ports -filter {direction == out}
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 3 -spread_type center -spacing 1.0 -pin {{PRDATA[0]} {PRDATA[1]} {PRDATA[2]} {PRDATA[3]} {PRDATA[4]} {PRDATA[5]} {PRDATA[6]} {PRDATA[7]} {PRDATA[8]} {PRDATA[9]} {PRDATA[10]} {PRDATA[11]} {PRDATA[12]} {PRDATA[13]} {PRDATA[14]} {PRDATA[15]} {PRDATA[16]} {PRDATA[17]} {PRDATA[18]} {PRDATA[19]} {PRDATA[20]} {PRDATA[21]} {PRDATA[22]} {PRDATA[23]} {PRDATA[24]} {PRDATA[25]} {PRDATA[26]} {PRDATA[27]} {PRDATA[28]} {PRDATA[29]} {PRDATA[30]} {PRDATA[31]} PREADY PSLVERR TIMERINT}
set_db assign_pins_edit_in_batch 0
set_db assign_pins_edit_in_batch 1
edit_pin -pin_width 0.07 -pin_depth 0.29 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 3 -spread_type center -spacing -0.95 -pin {{PRDATA[0]} {PRDATA[1]} {PRDATA[2]} {PRDATA[3]} {PRDATA[4]} {PRDATA[5]} {PRDATA[6]} {PRDATA[7]} {PRDATA[8]} {PRDATA[9]} {PRDATA[10]} {PRDATA[11]} {PRDATA[12]} {PRDATA[13]} {PRDATA[14]} {PRDATA[15]} {PRDATA[16]} {PRDATA[17]} {PRDATA[18]} {PRDATA[19]} {PRDATA[20]} {PRDATA[21]} {PRDATA[22]} {PRDATA[23]} {PRDATA[24]} {PRDATA[25]} {PRDATA[26]} {PRDATA[27]} {PRDATA[28]} {PRDATA[29]} {PRDATA[30]} {PRDATA[31]} PREADY PSLVERR TIMERINT}
set_db assign_pins_edit_in_batch 0
gui_fit
=============================================================================
set_db assign_pins_edit_in_batch 1
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 2 -spread_type center -spacing 0.19 -pin PWRITE
set_db assign_pins_edit_in_batch 0
=============================================================================
check_pin_assignment
legalize_pins -pins * -move_fixed_pins
check_pin_assignment
=============================================================================
# Add Rings
set_db add_rings_target default
set_db add_rings_extend_over_row 0
set_db add_rings_ignore_rows 0
set_db add_rings_avoid_short 0
set_db add_rings_skip_shared_inner_ring none
set_db add_rings_stacked_via_top_layer Metal9
set_db add_rings_stacked_via_bottom_layer Metal1
set_db add_rings_via_using_exact_crossover_size 1
set_db add_rings_orthogonal_only 1
set_db add_rings_skip_via_on_pin standardcell
set_db add_rings_skip_via_on_wire_shape noshape
add_rings -nets {VDD VSS} -type core_rings -follow core -layer {top Metal1 bottom Metal1 left Metal2 right Metal2} -width {top 0.5 bottom 0.5 left 0.5 right 0.5} -spacing {top 0.1 bottom 0.1 left 0.15 right 0.15} -offset {top 0.5 bottom 0.5 left 0.5 right 0.5} -center 0 -extend_corners {} -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
=============================================================================
# Add Stripes
set_db add_stripes_ignore_block_check 0
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only 0
set_db add_stripes_rows_without_stripes_only 0
set_db add_stripes_extend_to_closest_target none
set_db add_stripes_stop_at_last_wire_for_area 0
set_db add_stripes_partial_set_through_domain 0
set_db add_stripes_ignore_non_default_domains 0
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer Metal9
set_db add_stripes_stacked_via_bottom_layer Metal1
set_db add_stripes_via_using_exact_crossover_size 0
set_db add_stripes_split_vias 0
set_db add_stripes_orthogonal_only 1
set_db add_stripes_allow_jog {padcore_ring block_ring}
eval_legacy { addStripe -nets {VDD VSS} -layer Metal1 -direction vertical -width 0.5 -spacing 0.1 -number_of_sets 5 -start_from left -switch_layer_over_obs false -max_same_layer_jog_length 2 -padcore_ring_top_layer_limit Metal9 -padcore_ring_bottom_layer_limit Metal1 -block_ring_top_layer_limit Metal9 -block_ring_bottom_layer_limit Metal1 -use_wire_group 0 -snap_wire_center_to_grid None -skip_via_on_pin { standardcell } -skip_via_on_wire_shape { noshape } }
=============================================================================
# Add Special Routes
set_db route_special_via_connect_to_shape noshape
route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { Metal1(1) Metal9(9) } -block_pin_target {nearest_target} -pad_pin_port_connect {all_port one_geom} -pad_pin_target {nearest_target} -core_pin_target {first_after_row_end} -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -crossover_via_layer_range { Metal1(1) Metal9(9) } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { Metal1(1) Metal9(9) }
=============================================================================
place_opt_design
=============================================================================
write_db place_opt_design
=============================================================================
create_clock_tree_spec
=============================================================================
clock_design
=============================================================================
write_db postCTSopt
=============================================================================
set_db route_design_with_timing_driven 0
set_db route_design_with_si_driven 0
route_design -global_detail
set_db route_design_reserve_space_for_multi_cut 1
set_db route_design_concurrent_minimize_via_count_effort high
get_multi_cpu_usage -local_cpu
get_multi_cpu_usage -cpu_per_remote_host
get_multi_cpu_usage -remote_host
set_db route_design_with_timing_driven 1
set_db route_design_with_si_driven 1
set_db route_design_with_timing_driven 1
set_db route_design_with_si_driven 1
route_design -global_detail
set_db route_design_reserve_space_for_multi_cut 1
set_db route_design_concurrent_minimize_via_count_effort high
set_db route_design_detail_post_route_spread_wire 0.500000
set_db route_design_detail_post_route_spread_wire auto
set_db route_design_with_si_driven 1
set_db route_design_with_timing_driven 1
reset_db route_design_concurrent_minimize_via_count_effort
reset_db route_design_reserve_space_for_multi_cut
reset_db route_design_detail_post_route_spread_wire
delete_drc_markers
=============================================================================
extract_rc
write_parasitics -spef_file apb_timer.spef -rc_corner rccorners
=============================================================================
set_db timing_analysis_type ocv
time_design -post_route
time_design -post_route -hold
=============================================================================
set_db check_implant 1
set_db check_drc_implant_across_rows 0
set_db check_drc_ndr_spacing 0
set_db check_drc_inside_via_def 0
set_db check_drc_exclude_pg_net 0
set_db check_drc_ignore_trial_route 0
set_db check_drc_report apb_timer.drc.rpt
set_db check_drc_limit 1000
check_drc
counter.view == sample mmmc file
create_library_set -name max_timing\
-timing ../lib/slow_vdd1v0_basicCells.lib
create_library_set -name min_timing\
-timing ../lib/fast_vdd1v0_basicCells.lib
create_timing_condition -name default_mapping_tc_2\
-library_sets min_timing
create_timing_condition -name default_mapping_tc_1\
-library_sets max_timing
create_rc_corner -name rccorners\
-cap_table ../captable/cln28hpl_1p10m+alrdl_5x2yu2yz_typical.capTbl\
-pre_route_res 1\
-post_route_res 1\
-pre_route_cap 1\
-post_route_cap 1\
-post_route_cross_cap 1\
-pre_route_clock_res 0\
-pre_route_clock_cap 0\
-qrc_tech ../QRC_Tech/gpdk045.tch
create_delay_corner -name max_delay\
-timing_condition {default_mapping_tc_1}\
-rc_corner rccorners
create_delay_corner -name min_delay\
-timing_condition {default_mapping_tc_2}\
-rc_corner rccorners
create_constraint_mode -name sdc_cons\
-sdc_files\
counter_sdc.sdc
create_analysis_view -name wc -constraint_mode sdc_cons -delay_corner max_delay
create_analysis_view -name bc -constraint_mode sdc_cons -delay_corner min_delay
set_analysis_view -setup wc -hold bc
Lint Summary in Cadence Genus: Detailed Explanation with RTL Examples
Lint summary
Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 0
Sequential clock pins with multiple clock waveforms 0
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 1
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 0
Outputs without clocked external delays 0
Inputs without external driver/transition 0
Outputs without external load 0
Exceptions with invalid timing start-/endpoints 0
Total: 1
1. Unconnected/logic driven clocks — 0
Meaning:
Clocks in your design should be driven by a dedicated clock source (like a PLL or oscillator) and connected properly. If a clock signal is not connected or driven by logic gates instead of a proper clock source, it can cause timing analysis issues.
Example:
wire clk;
assign clk = a & b; // Clock driven by logic (not recommended)
This is flagged because a clock should not be generated by combinational logic like AND gates.
2. Sequential data pins driven by a clock signal — 0
Meaning:
Input data pins to sequential elements (flip-flops) should not be driven directly by a clock signal. Data inputs should be valid data, not clocks.
Example:
always @(posedge clk) begin
dff <= clk; // wrong: data driven by clock signal itself
end
Here, the data input is connected to the clock, which is wrong.
3. Sequential clock pins without clock waveform — 0
Meaning:
Clock pins of sequential elements (like FFs) should have defined clock waveforms (timing info). If the timing tool doesn’t have waveform info, it cannot analyze timing properly.
Example:
If your constraints miss defining the clock waveform (like period, duty cycle), the tool flags this.
4. Sequential clock pins with multiple clock waveforms — 0
Meaning:
A single clock pin should have one clock waveform definition. Multiple conflicting clock waveforms can confuse timing analysis.
Example:
If you define the clock period twice with different values for the same clock, you get this warning.
5. Generated clocks without clock waveform — 0
Meaning:
Clocks generated inside the design (e.g., from clock dividers) must have timing waveforms defined for the tool.
Example:
If a clock divider generates a clock but no period or waveform is provided, this flag occurs.
6. Generated clocks with incompatible options — 0
Meaning:
Generated clocks might have conflicting properties (like phase, duty cycle) that don’t match the source clock.
Example:
If a generated clock is defined with a 50% duty cycle but source clock is 30%, or if phase shift definitions contradict.
7. Generated clocks with multi-master clock — 0
Meaning:
A generated clock should have a single master clock source. If multiple clocks try to drive the same generated clock net, it causes ambiguity.
8. Paths constrained with different clocks — 0
Meaning:
A timing path should be constrained with one clock domain. If different constraints specify different clocks on the same path, it’s a problem.
9. Loop-breaking cells for combinational feedback — 0
Meaning:
Combinational loops (feedback paths without registers) are illegal in synchronous design. Loop-breaking cells are inserted to avoid infinite loops during timing analysis.
10. Nets with multiple drivers — 0
Meaning:
A net (wire) should have only one driver. Multiple drivers cause conflicts and possible glitches.
Example:
assign a = b;
assign a = c; // two drivers for a
This causes multiple drivers.
11. Timing exceptions with no effect — 1
Meaning:
Timing exceptions (like false paths, multicycle paths) defined in constraints but not affecting any timing paths. This is a warning to clean up unnecessary constraints.
Example:
If you declare a false path between two signals but no path exists, it’s flagged.
12. Suspicious multi_cycle exceptions — 0
Meaning:
multi-cycle paths allow more than one clock cycle for data to propagate. Suspicious ones may be incorrectly defined or inconsistent.
13. Pins/ports with conflicting case constants — 0
Meaning:
Pins or ports defined with conflicting constant logic levels (e.g., input tied to 0 in one place and 1 in another) cause issues.
14. Inputs without clocked external delays — 0
Meaning:
External input delays specify timing for signals coming from outside the chip. Missing delays for inputs can reduce accuracy of timing analysis.
15. Outputs without clocked external delays — 0
Meaning:
Outputs should also have delays defined to model external load or environment.
16. Inputs without external driver/transition — 0
Meaning:
Input pins must have driver and transition info defined to simulate realistic timing.
17. Outputs without external load — 0
Meaning:
Outputs should have defined load capacitance or equivalent for proper timing.
18. Exceptions with invalid timing start-/endpoints — 0
Meaning:
Timing exceptions (like false paths) must have valid start and end points in constraints. If invalid, they are ignored or flagged.
Code Snippets for each:
1. Unconnected/logic driven clocks
Verilog (bad clock driven by logic):
wire clk;
assign clk = a & b; // Clock driven by logic - bad practice
2. Sequential data pins driven by a clock signal
Verilog (wrong data input driven by clock):
always @(posedge clk) begin
q <= clk; // data input driven by clock signal - incorrect
end
3. Sequential clock pins without clock waveform
SDC (missing waveform info):
create_clock -name clk -period 10 [get_ports clk]
// No waveform specified, causes issue in some tools
Correct with waveform:
create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]
4. Sequential clock pins with multiple clock waveforms
SDC (conflicting clocks on same port):
create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]
create_clock -name clk -period 8 -waveform {0 4} [get_ports clk] # Conflicts
5. Generated clocks without clock waveform
SDC (missing waveform for generated clock):
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins clk_div2]
// Missing waveform option leads to warning
Correct:
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 -waveform {0 10} [get_pins clk_div2]
6. Generated clocks with incompatible options
SDC (conflicting duty cycles):
create_clock -name clk -period 10 -waveform {0 4} [get_ports clk] # 40% duty
create_generated_clock -name gen_clk -source [get_ports clk] -multiply_by 1 -divide_by 1 -waveform {0 5} [get_pins gen_clk] # 50% duty -> conflict
7. Generated clocks with multi-master clock
SDC (generated clock driven by multiple clocks):
create_generated_clock -name gen_clk -source [get_ports clk1] [get_pins gen_clk]
create_generated_clock -name gen_clk -source [get_ports clk2] [get_pins gen_clk] # Multi-master source
8. Paths constrained with different clocks
SDC (conflicting constraints on same path):
set_multicycle_path -setup 2 -from [get_clocks clk1] -to [get_clocks clk1]
set_multicycle_path -setup 1 -from [get_clocks clk2] -to [get_clocks clk1] # Conflicts on same path
9. Loop-breaking cells for combinational feedback
Verilog (combinational loop example):
wire a;
assign a = ~a; // Combinational feedback loop, illegal
Loop-breaking cell (special flip-flop or latch inserted manually or by tool) is required to break this.
10. Nets with multiple drivers
Verilog (multiple drivers):
wire a;
assign a = b;
assign a = c; // Multiple drivers on wire 'a' - illegal
11. Timing exceptions with no effect
SDC (false path that doesn't exist):
set_false_path -from [get_ports non_existing_port] -to [get_ports another_port]
Since the path doesn't exist, this has no effect.
12. Suspicious multi_cycle exceptions
SDC (multi-cycle path with unusual constraints):
set_multicycle_path -setup 0 -from [get_clocks clk] -to [get_clocks clk]
-setup 0 is suspicious because multi-cycle should be >=1.
13. Pins/ports with conflicting case constants
Verilog (conflicting constants):
wire in;
assign in = 1'b0; // Port tied to zero here
// Elsewhere assigned 1'b1 causing conflict
14. Inputs without clocked external delays
SDC (missing input delay):
# No input delay specified for input port 'data_in'
// Add with:
set_input_delay -clock clk 5 [get_ports data_in]
15. Outputs without clocked external delays
SDC (missing output delay):
# No output delay specified for output port 'data_out'
// Add with:
set_output_delay -clock clk 3 [get_ports data_out]
16. Inputs without external driver/transition
SDC (missing transition on inputs):
# No transition specified on input ports
set_driving_cell -lib_cell INV_X1 [get_ports data_in]
set_input_transition 1.0 [get_ports data_in]
17. Outputs without external load
SDC (missing output load):
# No load specified on output ports
set_load 10 [get_ports data_out]
18. Exceptions with invalid timing start-/endpoints
SDC (invalid false path endpoints):
set_false_path -from [get_ports invalid_port] -to [get_ports data_out] # invalid startpoint
apb_timer_placement.def
###############################################################
# Generated by:
# OS:
# Generated on:
# Design: apb_timer
# Command: defOut -floorplan -netlist -routing apb_timer_placement.def
###############################################################
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN apb_timer ;
UNITS DISTANCE MICRONS 2000 ;
PROPERTYDEFINITIONS
NET alpha_value REAL ;
COMPONENTPIN designRuleWidth REAL ;
DESIGN FE_CORE_BOX_LL_X REAL 2.000 ;
DESIGN FE_CORE_BOX_UR_X REAL 61.800 ;
DESIGN FE_CORE_BOX_LL_Y REAL 2.090 ;
DESIGN FE_CORE_BOX_UR_Y REAL 55.100 ;
END PROPERTYDEFINITIONS
DIEAREA ( 0 0 ) ( 127600 114380 ) ;
ROW ROW_0 CoreSite 4000 4180 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_1 CoreSite 4000 7600 N DO 299 BY 1 STEP 400 0
;
ROW ROW_2 CoreSite 4000 11020 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_3 CoreSite 4000 14440 N DO 299 BY 1 STEP 400 0
;
ROW ROW_4 CoreSite 4000 17860 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_5 CoreSite 4000 21280 N DO 299 BY 1 STEP 400 0
;
ROW ROW_6 CoreSite 4000 24700 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_7 CoreSite 4000 28120 N DO 299 BY 1 STEP 400 0
;
ROW ROW_8 CoreSite 4000 31540 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_9 CoreSite 4000 34960 N DO 299 BY 1 STEP 400 0
;
ROW ROW_10 CoreSite 4000 38380 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_11 CoreSite 4000 41800 N DO 299 BY 1 STEP 400 0
;
ROW ROW_12 CoreSite 4000 45220 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_13 CoreSite 4000 48640 N DO 299 BY 1 STEP 400 0
;
ROW ROW_14 CoreSite 4000 52060 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_15 CoreSite 4000 55480 N DO 299 BY 1 STEP 400 0
;
ROW ROW_16 CoreSite 4000 58900 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_17 CoreSite 4000 62320 N DO 299 BY 1 STEP 400 0
;
ROW ROW_18 CoreSite 4000 65740 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_19 CoreSite 4000 69160 N DO 299 BY 1 STEP 400 0
;
ROW ROW_20 CoreSite 4000 72580 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_21 CoreSite 4000 76000 N DO 299 BY 1 STEP 400 0
;
ROW ROW_22 CoreSite 4000 79420 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_23 CoreSite 4000 82840 N DO 299 BY 1 STEP 400 0
;
ROW ROW_24 CoreSite 4000 86260 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_25 CoreSite 4000 89680 N DO 299 BY 1 STEP 400 0
;
ROW ROW_26 CoreSite 4000 93100 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_27 CoreSite 4000 96520 N DO 299 BY 1 STEP 400 0
;
ROW ROW_28 CoreSite 4000 99940 FS DO 299 BY 1 STEP 400 0
;
ROW ROW_29 CoreSite 4000 103360 N DO 299 BY 1 STEP 400 0
;
ROW ROW_30 CoreSite 4000 106780 FS DO 299 BY 1 STEP 400 0
;
TRACKS X 200 DO 319 STEP 400 LAYER Metal9 ;
TRACKS Y 950 DO 150 STEP 760 LAYER Metal9 ;
TRACKS Y 760 DO 200 STEP 570 LAYER Metal8 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal8 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal7 ;
TRACKS Y 760 DO 200 STEP 570 LAYER Metal7 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal6 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal6 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal5 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal5 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal4 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal4 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal3 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal3 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal2 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal2 ;
TRACKS X 200 DO 319 STEP 400 LAYER Metal1 ;
TRACKS Y 190 DO 301 STEP 380 LAYER Metal1 ;
GCELLGRID Y 0 DO 2 STEP 190 ;
GCELLGRID Y 190 DO 31 STEP 3800 ;
GCELLGRID Y 114190 DO 2 STEP 190 ;
GCELLGRID X 0 DO 2 STEP 200 ;
GCELLGRID X 200 DO 32 STEP 4000 ;
GCELLGRID X 124200 DO 2 STEP 3400 ;
VIAS 3 ;
- M2_M1_1
+ VIARULE M2_M1
+ CUTSIZE 140 140
+ LAYERS Metal1 Via1 Metal2
+ CUTSPACING 220 140
+ ENCLOSURE 70 10 70 10
+ ROWCOL 4 3
;
- M2_M1_2
+ VIARULE M2_M1
+ CUTSIZE 140 140
+ LAYERS Metal1 Via1 Metal2
+ CUTSPACING 140 140
+ ENCLOSURE 10 60 10 60
+ ROWCOL 1 4
;
- M2_M1_3
+ VIARULE M2_M1
+ CUTSIZE 140 140
+ LAYERS Metal1 Via1 Metal2
+ CUTSPACING 140 140
+ ENCLOSURE 150 50 150 50
+ ROWCOL 1 3
;
END VIAS
COMPONENTS 504 ;
- FE_OFC182_PRDATA_25 INVX20 + SOURCE TIMING + PLACED ( 115200 21280 ) N
;
- FE_OFC181_PRDATA_25 INVX1 + SOURCE TIMING + PLACED ( 115200 11020 ) FS
;
- FE_OFC180_PRDATA_2 INVX20 + SOURCE TIMING + PLACED ( 115200 106780 ) FS
;
- FE_OFC179_PRDATA_2 INVX1 + SOURCE TIMING + PLACED ( 107200 106780 ) FS
;
- FE_OFC178_PRDATA_5 INVX20 + SOURCE TIMING + PLACED ( 107600 89680 ) N
;
- FE_OFC177_PRDATA_5 INVX1 + SOURCE TIMING + PLACED ( 108000 96520 ) N
;
- FE_OFC176_PRDATA_22 INVX20 + SOURCE TIMING + PLACED ( 115200 41800 ) N
;
- FE_OFC175_PRDATA_22 INVX1 + SOURCE TIMING + PLACED ( 108000 45220 ) FS
;
- FE_OFC174_PRDATA_31 INVX20 + SOURCE TIMING + PLACED ( 115200 4180 ) FS
;
- FE_OFC173_PRDATA_31 INVX1 + SOURCE TIMING + PLACED ( 107600 4180 ) FS
;
- FE_OFC172_PRDATA_8 INVX20 + SOURCE TIMING + PLACED ( 100800 82840 ) N
;
- FE_OFC171_PRDATA_8 INVX1 + SOURCE TIMING + PLACED ( 108400 82840 ) N
;
- FE_OFC170_PRDATA_6 INVX20 + SOURCE TIMING + PLACED ( 107600 86260 ) FS
;
- FE_OFC169_PRDATA_6 INVX1 + SOURCE TIMING + PLACED ( 100800 93100 ) FS
;
- FE_OFC168_PRDATA_19 INVX20 + SOURCE TIMING + PLACED ( 115200 52060 ) FS
;
- FE_OFC167_PRDATA_19 INVX1 + SOURCE TIMING + PLACED ( 101200 48640 ) N
;
- FE_OFC166_PRDATA_3 INVX20 + SOURCE TIMING + PLACED ( 103200 103360 ) N
;
- FE_OFC165_PRDATA_3 INVX1 + SOURCE TIMING + PLACED ( 84000 106780 ) FS
;
- FE_OFC164_PRDATA_4 INVX20 + SOURCE TIMING + PLACED ( 100000 99940 ) FS
;
- FE_OFC163_PRDATA_4 INVX1 + SOURCE TIMING + PLACED ( 107600 99940 ) FS
;
- FE_OFC162_PRDATA_9 INVX20 + SOURCE TIMING + PLACED ( 115200 76000 ) N
;
- FE_OFC161_PRDATA_9 INVX1 + SOURCE TIMING + PLACED ( 108000 79420 ) FS
;
- FE_OFC160_PRDATA_13 INVX20 + SOURCE TIMING + PLACED ( 100400 72580 ) FS
;
- FE_OFC159_PRDATA_13 INVX1 + SOURCE TIMING + PLACED ( 108000 69160 ) N
;
- FE_OFC158_PRDATA_18 INVX20 + SOURCE TIMING + PLACED ( 115200 55480 ) N
;
- FE_OFC157_PRDATA_18 INVX1 + SOURCE TIMING + PLACED ( 107600 55480 ) N
;
- FE_OFC156_PRDATA_21 INVX20 + SOURCE TIMING + PLACED ( 100400 45220 ) FS
;
- FE_OFC155_PRDATA_21 INVX1 + SOURCE TIMING + PLACED ( 107600 52060 ) FS
;
- FE_OFC154_PRDATA_7 INVX20 + SOURCE TIMING + PLACED ( 115200 86260 ) FS
;
- FE_OFC153_PRDATA_7 INVX1 + SOURCE TIMING + PLACED ( 108400 93100 ) FS
;
- FE_OFC152_PRDATA_15 INVX20 + SOURCE TIMING + PLACED ( 115200 62320 ) N
;
- FE_OFC151_PRDATA_15 INVX1 + SOURCE TIMING + PLACED ( 107600 62320 ) N
;
- FE_OFC150_PRDATA_16 INVX20 + SOURCE TIMING + PLACED ( 115200 58900 ) FS
;
- FE_OFC149_PRDATA_16 INVX1 + SOURCE TIMING + PLACED ( 107200 58900 ) FS
;
- FE_OFC148_PRDATA_24 INVX20 + SOURCE TIMING + PLACED ( 115200 34960 ) N
;
- FE_OFC147_PRDATA_24 INVX1 + SOURCE TIMING + PLACED ( 108000 17860 ) FS
;
- FE_OFC146_PRDATA_28 INVX20 + SOURCE TIMING + PLACED ( 115200 28120 ) N
;
- FE_OFC145_PRDATA_28 INVX1 + SOURCE TIMING + PLACED ( 107600 28120 ) N
;
- FE_OFC144_PRDATA_30 INVX20 + SOURCE TIMING + PLACED ( 115200 7600 ) N
;
- FE_OFC143_PRDATA_30 INVX1 + SOURCE TIMING + PLACED ( 99200 4180 ) FS
;
- FE_OFC142_PRDATA_11 INVX20 + SOURCE TIMING + PLACED ( 115200 89680 ) N
;
- FE_OFC141_PRDATA_11 INVX1 + SOURCE TIMING + PLACED ( 108000 72580 ) FS
;
- FE_OFC140_PRDATA_14 INVX20 + SOURCE TIMING + PLACED ( 115200 65740 ) FS
;
- FE_OFC139_PRDATA_14 INVX1 + SOURCE TIMING + PLACED ( 106800 65740 ) FS
;
- FE_OFC138_PRDATA_26 INVX20 + SOURCE TIMING + PLACED ( 115200 48640 ) N
;
- FE_OFC137_PRDATA_26 INVX1 + SOURCE TIMING + PLACED ( 108400 31540 ) FS
;
- FE_OFC136_PRDATA_29 INVX20 + SOURCE TIMING + PLACED ( 107600 21280 ) N
;
- FE_OFC135_PRDATA_29 INVX1 + SOURCE TIMING + PLACED ( 108400 24700 ) FS
;
- FE_OFC134_PRDATA_9 INVX1 + SOURCE TIMING + PLACED ( 102800 86260 ) FS
;
- FE_OFC133_PRDATA_9 INVX1 + SOURCE TIMING + PLACED ( 96000 79420 ) FS
;
- FE_OFC132_PRDATA_11 INVX1 + SOURCE TIMING + PLACED ( 102800 69160 ) N
;
- FE_OFC131_PRDATA_11 INVX1 + SOURCE TIMING + PLACED ( 94400 72580 ) FS
;
- FE_OFC130_PRDATA_13 INVX1 + SOURCE TIMING + PLACED ( 102800 79420 ) FS
;
- FE_OFC129_PRDATA_13 INVX1 + SOURCE TIMING + PLACED ( 90400 65740 ) FS
;
- FE_OFC128_PRDATA_14 INVX1 + SOURCE TIMING + PLACED ( 100800 65740 ) FS
;
- FE_OFC127_PRDATA_14 INVX1 + SOURCE TIMING + PLACED ( 89200 62320 ) N
;
- FE_OFC126_PRDATA_16 INVX1 + SOURCE TIMING + PLACED ( 101600 58900 ) FS
;
- FE_OFC125_PRDATA_16 INVX1 + SOURCE TIMING + PLACED ( 94400 58900 ) FS
;
- FE_OFC124_PRDATA_21 INVX1 + SOURCE TIMING + PLACED ( 102000 52060 ) FS
;
- FE_OFC123_PRDATA_21 INVX1 + SOURCE TIMING + PLACED ( 95200 52060 ) FS
;
- FE_OFC122_PRDATA_7 INVX1 + SOURCE TIMING + PLACED ( 96000 93100 ) FS
;
- FE_OFC121_PRDATA_7 INVX1 + SOURCE TIMING + PLACED ( 98800 89680 ) N
;
- FE_OFC120_PRDATA_15 INVX1 + SOURCE TIMING + PLACED ( 102400 62320 ) N
;
- FE_OFC119_PRDATA_15 INVX1 + SOURCE TIMING + PLACED ( 95600 62320 ) N
;
- FE_OFC118_PRDATA_26 INVX1 + SOURCE TIMING + PLACED ( 103600 24700 ) FS
;
- FE_OFC117_PRDATA_26 INVX1 + SOURCE TIMING + PLACED ( 97200 24700 ) FS
;
- FE_OFC116_PRDATA_28 INVX1 + SOURCE TIMING + PLACED ( 100400 28120 ) N
;
- FE_OFC115_PRDATA_28 INVX1 + SOURCE TIMING + PLACED ( 94400 31540 ) FS
;
- FE_OFC114_PRDATA_18 INVX1 + SOURCE TIMING + PLACED ( 103200 38380 ) FS
;
- FE_OFC113_PRDATA_18 INVX1 + SOURCE TIMING + PLACED ( 97600 34960 ) N
;
- FE_OFC112_PRDATA_29 INVX1 + SOURCE TIMING + PLACED ( 102800 17860 ) FS
;
- FE_OFC111_PRDATA_29 INVX1 + SOURCE TIMING + PLACED ( 96400 21280 ) N
;
- FE_OFC110_PRDATA_4 INVX1 + SOURCE TIMING + PLACED ( 95200 99940 ) FS
;
- FE_OFC109_PRDATA_4 INVX1 + SOURCE TIMING + PLACED ( 94400 103360 ) N
;
- FE_OFC108_PRDATA_30 INVX1 + SOURCE TIMING + PLACED ( 94400 4180 ) FS
;
- FE_OFC107_PRDATA_30 INVX1 + SOURCE TIMING + PLACED ( 59600 4180 ) FS
;
- FE_OFC106_PRDATA_24 INVX1 + SOURCE TIMING + PLACED ( 116000 17860 ) FS
;
- FE_OFC105_PRDATA_24 INVX1 + SOURCE TIMING + PLACED ( 90400 11020 ) FS
;
- FE_OFC104_PRDATA_8 INVX1 + SOURCE TIMING + PLACED ( 116000 82840 ) N
;
- FE_OFC103_PRDATA_8 INVX1 + SOURCE TIMING + PLACED ( 94400 82840 ) N
;
- FE_OFC102_PRDATA_6 INVX1 + SOURCE TIMING + PLACED ( 86800 93100 ) FS
;
- FE_OFC101_PRDATA_6 INVX1 + SOURCE TIMING + PLACED ( 74400 93100 ) FS
;
- FE_OFC100_PRDATA_3 INVX1 + SOURCE TIMING + PLACED ( 77600 103360 ) N
;
- FE_OFC99_PRDATA_3 INVX1 + SOURCE TIMING + PLACED ( 66800 103360 ) N
;
- FE_OFC98_PRDATA_5 INVX1 + SOURCE TIMING + PLACED ( 102800 96520 ) N
;
- FE_OFC97_PRDATA_5 INVX1 + SOURCE TIMING + PLACED ( 88800 96520 ) N
;
- FE_OFC96_PRDATA_22 INVX1 + SOURCE TIMING + PLACED ( 108800 48640 ) N
;
- FE_OFC95_PRDATA_22 INVX1 + SOURCE TIMING + PLACED ( 101200 41800 ) N
;
- FE_OFC94_PRDATA_2 INVX1 + SOURCE TIMING + PLACED ( 100800 106780 ) FS
;
- FE_OFC93_PRDATA_2 INVX1 + SOURCE TIMING + PLACED ( 94400 106780 ) FS
;
- FE_OFC92_PRDATA_19 INVX1 + SOURCE TIMING + PLACED ( 96800 38380 ) FS
;
- FE_OFC91_PRDATA_19 INVX1 + SOURCE TIMING + PLACED ( 90400 34960 ) N
;
- FE_OFC90_PRDATA_25 INVX1 + SOURCE TIMING + PLACED ( 108000 7600 ) N
;
- FE_OFC89_PRDATA_25 INVX1 + SOURCE TIMING + PLACED ( 87200 7600 ) N
;
- FE_OFC88_PRDATA_31 INVX1 + SOURCE TIMING + PLACED ( 101200 7600 ) N
;
- FE_OFC87_PRDATA_31 INVX1 + SOURCE TIMING + PLACED ( 94400 7600 ) N
;
- FE_OFC86_PRDATA_12 INVX20 + SOURCE TIMING + PLACED ( 95200 69160 ) N
;
- FE_OFC85_PRDATA_12 INVX1 + SOURCE TIMING + PLACED ( 87600 69160 ) N
;
- FE_OFC84_PRDATA_10 INVX20 + SOURCE TIMING + PLACED ( 104400 76000 ) N
;
- FE_OFC83_PRDATA_10 INVX1 + SOURCE TIMING + PLACED ( 96000 76000 ) N
;
- FE_OFC82_PRDATA_20 INVX20 + SOURCE TIMING + PLACED ( 107600 41800 ) N
;
- FE_OFC81_PRDATA_20 INVX1 + SOURCE TIMING + PLACED ( 108400 38380 ) FS
;
- FE_OFC80_PRDATA_17 INVX20 + SOURCE TIMING + PLACED ( 99200 55480 ) N
;
- FE_OFC79_PRDATA_17 INVX1 + SOURCE TIMING + PLACED ( 90400 55480 ) N
;
- FE_OFC78_PRDATA_0 INVX20 + SOURCE TIMING + PLACED ( 115200 99940 ) FS
;
- FE_OFC77_PRDATA_0 INVX1 + SOURCE TIMING + PLACED ( 95200 96520 ) N
;
- FE_OFC76_PRDATA_23 INVX20 + SOURCE TIMING + PLACED ( 104000 34960 ) N
;
- FE_OFC75_PRDATA_23 INVX1 + SOURCE TIMING + PLACED ( 65600 38380 ) FS
;
- FE_OFC74_PRDATA_27 INVX20 + SOURCE TIMING + PLACED ( 100400 31540 ) FS
;
- FE_OFC73_PRDATA_27 INVX1 + SOURCE TIMING + PLACED ( 89200 28120 ) N
;
- FE_OFC72_PRDATA_1 INVX20 + SOURCE TIMING + PLACED ( 115200 103360 ) N
;
- FE_OFC71_PRDATA_1 INVX1 + SOURCE TIMING + PLACED ( 84000 99940 ) FS
;
- FE_OFC70_TIMERINT INVX20 + SOURCE TIMING + PLACED ( 115200 14440 ) N
;
- FE_OFC69_TIMERINT INVX1 + SOURCE TIMING + PLACED ( 108400 14440 ) N
;
- FE_OFC68_TIMERINT INVX1 + SOURCE TIMING + PLACED ( 103200 21280 ) N
;
- FE_OFC67_TIMERINT INVX1 + SOURCE TIMING + PLACED ( 99600 31540 ) FS
;
- FE_OFC11_TIMERINT INVX1 + SOURCE TIMING + PLACED ( 26000 45220 ) FS
;
- FE_OFC10_TIMERINT INVX1 + SOURCE TIMING + PLACED ( 24000 48640 ) N
;
- FE_OFC0_PRESETn BUFX3 + SOURCE TIMING + PLACED ( 9600 7600 ) N
;
- RC_CG_HIER_INST0/RC_CGIC_INST TLATNTSCAX2 + PLACED ( 59600 58900 ) FS
;
- RC_CG_HIER_INST1/RC_CGIC_INST TLATNTSCAX2 + PLACED ( 36000 96520 ) N
;
- RC_CG_HIER_INST2/RC_CGIC_INST TLATNTSCAX2 + PLACED ( 25200 58900 ) FS
;
- RC_CG_HIER_INST3/RC_CGIC_INST TLATNTSCAX2 + PLACED ( 26000 93100 ) FS
;
- RC_CG_HIER_INST4/RC_CGIC_INST TLATNTSCAX2 + PLACED ( 39200 65740 ) FS
;
- g3185 INVX2 + PLACED ( 42800 38380 ) FS
;
- ext_in_delay_reg DFFRX2 + PLACED ( 34000 82840 ) N
;
- ext_in_sync1_reg DFFRHQX2 + PLACED ( 31600 106780 ) FS
;
- ext_in_sync2_reg DFFRHQX2 + PLACED ( 31600 99940 ) FS
;
- read_mux_byte0_reg_reg\[0\] DFFRHQX2 + PLACED ( 20400 79420 ) FS
;
- read_mux_byte0_reg_reg\[1\] DFFRHQX2 + PLACED ( 17200 99940 ) FS
;
- read_mux_byte0_reg_reg\[2\] DFFRHQX2 + PLACED ( 15600 96520 ) N
;
- read_mux_byte0_reg_reg\[3\] DFFRHQX2 + PLACED ( 26800 89680 ) N
;
- read_mux_byte0_reg_reg\[4\] DFFRHQX2 + PLACED ( 10400 89680 ) N
;
- read_mux_byte0_reg_reg\[5\] DFFRHQX2 + PLACED ( 10800 93100 ) FS
;
- read_mux_byte0_reg_reg\[6\] DFFRHQX2 + PLACED ( 22800 86260 ) FS
;
- read_mux_byte0_reg_reg\[7\] DFFRHQX2 + PLACED ( 12400 86260 ) FS
;
- reg_ctrl_reg\[0\] DFFRHQX2 + PLACED ( 38000 55480 ) N
;
- reg_ctrl_reg\[1\] DFFRHQX2 + PLACED ( 36000 62320 ) N
;
- reg_reload_val_reg\[0\] DFFRHQX2 + PLACED ( 24000 41800 ) N
;
- reg_reload_val_reg\[1\] DFFRHQX2 + PLACED ( 46800 62320 ) N
;
- reg_reload_val_reg\[2\] DFFRHQX2 + PLACED ( 39200 69160 ) N
;
- reg_reload_val_reg\[3\] DFFRHQX2 + PLACED ( 38800 58900 ) FS
;
- reg_reload_val_reg\[4\] DFFRHQX2 + PLACED ( 53600 65740 ) FS
;
- reg_reload_val_reg\[5\] DFFRHQX2 + PLACED ( 55600 69160 ) N
;
- reg_reload_val_reg\[6\] DFFRHQX2 + PLACED ( 60400 62320 ) N
;
- reg_reload_val_reg\[7\] DFFRHQX2 + PLACED ( 65200 65740 ) FS
;
- reg_reload_val_reg\[8\] DFFRHQX2 + PLACED ( 77200 65740 ) FS
;
- reg_reload_val_reg\[9\] DFFRHQX2 + PLACED ( 71200 69160 ) N
;
- reg_reload_val_reg\[10\] DFFRHQX2 + PLACED ( 79600 72580 ) FS
;
- reg_reload_val_reg\[11\] DFFRHQX2 + PLACED ( 70000 62320 ) N
;
- reg_reload_val_reg\[12\] DFFRHQX2 + PLACED ( 69200 58900 ) FS
;
- reg_reload_val_reg\[13\] DFFRHQX2 + PLACED ( 66000 45220 ) FS
;
- reg_reload_val_reg\[14\] DFFRHQX2 + PLACED ( 75600 38380 ) FS
;
- reg_reload_val_reg\[15\] DFFRHQX2 + PLACED ( 76000 34960 ) N
;
- reg_reload_val_reg\[16\] DFFRHQX2 + PLACED ( 81200 4180 ) FS
;
- reg_reload_val_reg\[17\] DFFRHQX2 + PLACED ( 66800 7600 ) N
;
- reg_reload_val_reg\[18\] DFFRHQX2 + PLACED ( 77200 7600 ) N
;
- reg_reload_val_reg\[19\] DFFRHQX2 + PLACED ( 74400 24700 ) FS
;
- reg_reload_val_reg\[20\] DFFRHQX2 + PLACED ( 65200 24700 ) FS
;
- reg_reload_val_reg\[21\] DFFRHQX2 + PLACED ( 66800 41800 ) N
;
- reg_reload_val_reg\[22\] DFFRHQX2 + PLACED ( 55600 45220 ) FS
;
- reg_reload_val_reg\[23\] DFFRHQX2 + PLACED ( 42000 34960 ) N
;
- reg_reload_val_reg\[24\] DFFRHQX2 + PLACED ( 66400 4180 ) FS
;
- reg_reload_val_reg\[25\] DFFRHQX2 + PLACED ( 50400 7600 ) N
;
- reg_reload_val_reg\[26\] DFFRHQX2 + PLACED ( 36000 4180 ) FS
;
- reg_reload_val_reg\[27\] DFFRHQX2 + PLACED ( 36800 14440 ) N
;
- reg_reload_val_reg\[28\] DFFRHQX2 + PLACED ( 26800 31540 ) FS
;
- reg_reload_val_reg\[29\] DFFRHQX2 + PLACED ( 20800 28120 ) N
;
- reg_reload_val_reg\[30\] DFFRHQX2 + PLACED ( 24800 4180 ) FS
;
- reg_reload_val_reg\[31\] DFFRHQX2 + PLACED ( 13600 4180 ) FS
;
- g4401__8780 OR2X1 + PLACED ( 65200 93100 ) FS
;
- g4402__4296 OR2X1 + PLACED ( 55200 93100 ) FS
;
- g4403__3772 OR2X1 + PLACED ( 51200 89680 ) N
;
- g4404__1474 OR2X1 + PLACED ( 42000 79420 ) FS
;
- g4405__4547 NOR2BX1 + PLACED ( 39600 89680 ) N
;
- g4406__9682 NOR2BX1 + PLACED ( 40800 93100 ) FS
;
- g4407__2683 NOR2BX1 + PLACED ( 20000 93100 ) FS
;
- g4408__1309 NOR2BX1 + PLACED ( 32000 79420 ) FS
;
- g4409__6877 OR2X1 + PLACED ( 49600 96520 ) N
;
- g4410__2900 OR2X1 + PLACED ( 69200 89680 ) N
;
- g4411__2391 OR2X1 + PLACED ( 67200 89680 ) N
;
- g4412__7675 OR2X1 + PLACED ( 46000 96520 ) N
;
- g4417__7118 NOR2BX1 + PLACED ( 28800 96520 ) N
;
- g4418__8757 NOR2BX1 + PLACED ( 37600 89680 ) N
;
- g4419__1786 NOR2BX1 + PLACED ( 36000 86260 ) FS
;
- g4420__5953 NOR2BX1 + PLACED ( 30800 96520 ) N
;
- g4425__5703 OAI21XL + PLACED ( 18800 82840 ) N
;
- g4426__7114 NAND2X1 + PLACED ( 27600 72580 ) FS
;
- g4427__5266 OAI2BB1X1 + PLACED ( 24000 52060 ) FS
;
- g4428__2250 OAI2BB1X1 + PLACED ( 14400 79420 ) FS
;
- g4430__2703 AOI221X1 + PLACED ( 6800 79420 ) FS
;
- g4431__5795 AOI221X1 + PLACED ( 10800 82840 ) N
;
- g4432__7344 OAI211X1 + PLACED ( 6800 86260 ) FS
;
- g4433__1840 OAI21XL + PLACED ( 10000 76000 ) N
;
- g4434__5019 AOI222X1 + PLACED ( 19200 55480 ) N
;
- g4435__1857 OAI21XL + PLACED ( 21600 72580 ) FS
;
- g4436__9906 OAI221X1 + PLACED ( 21600 69160 ) N
;
- g4444__1309 NAND2X4 + PLACED ( 38000 41800 ) N
;
- g4461__1840 MX2XL + PLACED ( 14800 72580 ) FS
;
- g4462__5019 NOR2BX1 + PLACED ( 81600 21280 ) N
;
- g4464__9906 NOR2BX1 + PLACED ( 32000 17860 ) FS
;
- g4466__4296 NOR2BX1 + PLACED ( 86400 79420 ) FS
;
- g4469__4547 NOR2BX1 + PLACED ( 52800 31540 ) FS
;
- g4470__9682 NOR2BX1 + PLACED ( 83600 82840 ) N
;
- g4473__6877 NOR2BX1 + PLACED ( 76000 86260 ) FS
;
- g4474__2900 NOR2BX1 + PLACED ( 38400 17860 ) FS
;
- g4476__7675 NOR2BX1 + PLACED ( 60800 34960 ) N
;
- g4477__7118 NOR2BX1 + PLACED ( 71600 86260 ) FS
;
- g4479__1786 NOR2BX1 + PLACED ( 38800 24700 ) FS
;
- g4480__5953 NOR2BX1 + PLACED ( 69600 86260 ) FS
;
- g4481__5703 NOR2BX1 + PLACED ( 66400 48640 ) N
;
- g4482__7114 NOR2BX1 + PLACED ( 65200 86260 ) FS
;
- g4483__5266 NOR2BX1 + PLACED ( 53200 93100 ) FS
;
- g4485__6083 NOR2BX1 + PLACED ( 55200 31540 ) FS
;
- g4488__7344 NOR2BX1 + PLACED ( 51600 82840 ) N
;
- g4489__1840 NOR2BX1 + PLACED ( 38400 34960 ) N
;
- g4490__5019 NOR2BX1 + PLACED ( 49600 82840 ) N
;
- g4491__1857 NOR2BX1 + PLACED ( 82000 76000 ) N
;
- g4492__9906 AOI22X1 + PLACED ( 6800 69160 ) N
;
- g4494__4296 NOR2BX1 + PLACED ( 42000 76000 ) N
;
- g4495__3772 NOR2BX1 + PLACED ( 83600 17860 ) FS
;
- g4499__2683 NOR2BX1 + PLACED ( 86800 17860 ) FS
;
- g4502__2900 NOR2BX1 + PLACED ( 79600 21280 ) N
;
- g4503__2391 NOR2BX1 + PLACED ( 46000 28120 ) N
;
- g4505__7118 NOR2BX1 + PLACED ( 49200 28120 ) N
;
- g4507__1786 NOR2BX1 + PLACED ( 84400 45220 ) FS
;
- g4509__5703 NOR2BX1 + PLACED ( 56800 17860 ) FS
;
- g4510__7114 NOR2BX1 + PLACED ( 83200 48640 ) N
;
- g4512__2250 NOR2BX1 + PLACED ( 80800 52060 ) FS
;
- g4514__2703 NOR2BX1 + PLACED ( 79600 58900 ) FS
;
- g4517__1840 NOR2BX1 + PLACED ( 65200 14440 ) N
;
- g4518__5019 NOR2BX1 + PLACED ( 46000 82840 ) N
;
- g4519__1857 AOI22X1 + PLACED ( 28400 65740 ) FS
;
- g4520__9906 AOI22X1 + PLACED ( 36000 58900 ) FS
;
- g4522__4296 NAND2X1 + PLACED ( 24400 76000 ) N
;
- g4523__3772 NOR2XL + PLACED ( 23600 62320 ) N
;
- g4524__1474 NAND2X1 + PLACED ( 31600 69160 ) N
;
- g4525__4547 NAND2BX1 + PLACED ( 30400 79420 ) FS
;
- g4527 INVX1 + PLACED ( 7200 82840 ) N
;
- g4528 INVX1 + PLACED ( 14800 76000 ) N
;
- g4531__2683 NAND2BX1 + PLACED ( 11200 62320 ) N
;
- g4532__1309 NAND3X1 + PLACED ( 6800 65740 ) FS
;
- g4533__6877 NOR2XL + PLACED ( 15600 69160 ) N
;
- g4534__2900 AND2X2 + PLACED ( 36000 79420 ) FS
;
- g4535 INVX1 + PLACED ( 20400 52060 ) FS
;
- g4536 INVX1 + PLACED ( 20400 65740 ) FS
;
- g4537 INVX1 + PLACED ( 11600 69160 ) N
;
- g4538__2391 NOR2XL + PLACED ( 17200 52060 ) FS
;
- g4539__7675 NAND2BX1 + PLACED ( 19200 62320 ) N
;
- g4540__7118 NOR2XL + PLACED ( 7200 52060 ) FS
;
- g4542 INVX1 + PLACED ( 7200 76000 ) N
;
- g4544__8757 NOR2XL + PLACED ( 20000 76000 ) N
;
- g4545__1786 OR4X1 + PLACED ( 9200 34960 ) N
;
- g4546__5953 NAND2BX1 + PLACED ( 7200 58900 ) FS
;
- g4547__5703 AND3XL + PLACED ( 12800 45220 ) FS
;
- g4548 INVX1 + PLACED ( 14800 48640 ) N
;
- g4551__5266 NOR2XL + PLACED ( 12000 38380 ) FS
;
- g4552__2250 AO21X1 + PLACED ( 11600 55480 ) N
;
- g4553__6083 NAND2BX1 + PLACED ( 31600 76000 ) N
;
- g4554__2703 AOI21XL + PLACED ( 16800 58900 ) FS
;
- g4555__5795 NAND3X1 + PLACED ( 7200 21280 ) N
;
- g4556__7344 NOR2XL + PLACED ( 36400 69160 ) N
;
- g4557__1840 NOR2XL + PLACED ( 11200 58900 ) FS
;
- g4559__5019 NOR2XL + PLACED ( 7200 48640 ) N
;
- g4560__1857 AND4XL + PLACED ( 10800 14440 ) N
;
- g4563__4296 NAND3BXL + PLACED ( 7200 31540 ) FS
;
- g4588 INVX1 + PLACED ( 29600 76000 ) N
;
- g4605__2683 NAND2BX1 + PLACED ( 7200 45220 ) FS
;
- g4607__1309 NAND2X1 + PLACED ( 6800 62320 ) N
;
- g4608__6877 NAND2X1 + PLACED ( 11200 52060 ) FS
;
- g4610__2900 OR2XL + PLACED ( 13600 41800 ) N
;
- g4611__2391 NOR2XL + PLACED ( 15600 65740 ) FS
;
- g4612__7675 NAND2BX1 + PLACED ( 7200 38380 ) FS
;
- g4613 INVX1 + PLACED ( 7200 103360 ) N
;
- g4614 INVX1 + PLACED ( 9200 41800 ) N
;
- g2__7118 NAND2BX4 + PLACED ( 28800 72580 ) FS
;
- g4647__8757 NOR2BX1 + PLACED ( 22000 58900 ) FS
;
- reg_curr_val_reg\[1\] SDFFRHQX1 + PLACED ( 42800 48640 ) N
;
- reg_curr_val_reg\[3\] SDFFRHQX1 + PLACED ( 47200 52060 ) FS
;
- reg_curr_val_reg\[4\] SDFFRHQX1 + PLACED ( 50000 86260 ) FS
;
- reg_curr_val_reg\[5\] SDFFRHQX1 + PLACED ( 55600 96520 ) N
;
- reg_curr_val_reg\[7\] SDFFRHQX1 + PLACED ( 68800 96520 ) N
;
- reg_curr_val_reg\[8\] SDFFRHQX1 + PLACED ( 72000 89680 ) N
;
- reg_curr_val_reg\[9\] SDFFRHQX1 + PLACED ( 89600 86260 ) FS
;
- reg_curr_val_reg\[10\] SDFFRHQX1 + PLACED ( 87600 89680 ) N
;
- reg_curr_val_reg\[11\] SDFFRHQX1 + PLACED ( 78000 86260 ) FS
;
- reg_curr_val_reg\[12\] SDFFRHQX1 + PLACED ( 68800 55480 ) N
;
- reg_curr_val_reg\[13\] SDFFRHQX1 + PLACED ( 90000 48640 ) N
;
- reg_curr_val_reg\[15\] SDFFRHQX1 + PLACED ( 84800 38380 ) FS
;
- reg_curr_val_reg\[17\] SDFFRHQX1 + PLACED ( 98000 11020 ) FS
;
- reg_curr_val_reg\[18\] SDFFRHQX1 + PLACED ( 96800 14440 ) N
;
- reg_curr_val_reg\[19\] SDFFRHQX1 + PLACED ( 76400 28120 ) N
;
- reg_curr_val_reg\[20\] SDFFRHQX1 + PLACED ( 66800 31540 ) FS
;
- reg_curr_val_reg\[21\] SDFFRHQX1 + PLACED ( 57600 55480 ) N
;
- reg_curr_val_reg\[22\] SDFFRHQX1 + PLACED ( 55200 48640 ) N
;
- reg_curr_val_reg\[23\] SDFFRHQX1 + PLACED ( 46000 41800 ) N
;
- reg_curr_val_reg\[24\] SDFFRHQX1 + PLACED ( 58800 17860 ) FS
;
- reg_curr_val_reg\[25\] SDFFRHQX1 + PLACED ( 50400 14440 ) N
;
- reg_curr_val_reg\[26\] SDFFRHQX1 + PLACED ( 40800 17860 ) FS
;
- reg_curr_val_reg\[27\] SDFFRHQX1 + PLACED ( 38800 31540 ) FS
;
- reg_curr_val_reg\[28\] SDFFRHQX1 + PLACED ( 17200 38380 ) FS
;
- reg_curr_val_reg\[29\] SDFFRHQX1 + PLACED ( 14400 31540 ) FS
;
- reg_curr_val_reg\[30\] SDFFRHQX1 + PLACED ( 13600 17860 ) FS
;
- reg_curr_val_reg\[31\] SDFFRHQX1 + PLACED ( 10400 11020 ) FS
;
- reg_timer_int_reg DFFRHQX2 + PLACED ( 26800 55480 ) N
;
- g4648 INVX1 + PLACED ( 88000 82840 ) N
;
- g4649 INVX1 + PLACED ( 37200 41800 ) N
;
- g4609 INVX1 + PLACED ( 86800 82840 ) N
;
- g4650 INVX1 + PLACED ( 73600 52060 ) FS
;
- g4651 INVX1 + PLACED ( 86800 48640 ) N
;
- g4652 INVX1 + PLACED ( 48400 55480 ) N
;
- g4653__1786 AOI222X1 + PLACED ( 75600 72580 ) FS
;
- g4654__5953 AOI222X1 + PLACED ( 36000 38380 ) FS
;
- g4615__5703 AOI222X1 + PLACED ( 78000 76000 ) N
;
- g4616__7114 AOI222X1 + PLACED ( 70000 52060 ) FS
;
- g4617__5266 AOI222X1 + PLACED ( 72800 48640 ) N
;
- g4618__2250 AOI222X1 + PLACED ( 48000 58900 ) FS
;
- g4619 INVX1 + PLACED ( 73600 86260 ) FS
;
- g4620 INVX1 + PLACED ( 52000 55480 ) N
;
- g4621 INVX1 + PLACED ( 55200 82840 ) N
;
- g4622 INVX1 + PLACED ( 61200 86260 ) FS
;
- g4623 INVX1 + PLACED ( 57200 79420 ) FS
;
- g4624 INVX1 + PLACED ( 71200 89680 ) N
;
- g4625 INVX1 + PLACED ( 48400 76000 ) N
;
- g4626__6083 AOI222X1 + PLACED ( 70000 76000 ) N
;
- g4627__2703 AOI222X1 + PLACED ( 52000 58900 ) FS
;
- g4628__5795 AOI222X1 + PLACED ( 55200 76000 ) N
;
- g4629__7344 AOI222X1 + PLACED ( 58800 76000 ) N
;
- g4630__1840 AOI222X1 + PLACED ( 65200 72580 ) FS
;
- g4631__5019 AOI222X1 + PLACED ( 66000 76000 ) N
;
- g4632__1857 AOI222X1 + PLACED ( 46000 72580 ) FS
;
- g4633 INVX1 + PLACED ( 68400 48640 ) N
;
- g4634 INVX1 + PLACED ( 87200 41800 ) N
;
- g4635 INVX1 + PLACED ( 85600 34960 ) N
;
- g4636 INVX1 + PLACED ( 89200 14440 ) N
;
- g4637 INVX1 + PLACED ( 90400 14440 ) N
;
- g4638 INVX1 + PLACED ( 88400 14440 ) N
;
- g4639 INVX1 + PLACED ( 75600 28120 ) N
;
- g4640 INVX1 + PLACED ( 68800 28120 ) N
;
- g4641 INVX1 + PLACED ( 81600 69160 ) N
;
- g4642__9906 AOI222X1 + PLACED ( 58800 38380 ) FS
;
- g4643__8780 AOI222X1 + PLACED ( 71200 38380 ) FS
;
- g4644__4296 AOI222X1 + PLACED ( 70800 34960 ) N
;
- g4645__3772 AOI222X1 + PLACED ( 77200 11020 ) FS
;
- g4646__1474 AOI222X1 + PLACED ( 72000 11020 ) FS
;
- g4655__4547 AOI222X1 + PLACED ( 74000 14440 ) N
;
- g4656__9682 AOI222X1 + PLACED ( 72000 28120 ) N
;
- g4657__2683 AOI222X1 + PLACED ( 65200 28120 ) N
;
- g4658__1309 AOI222X1 + PLACED ( 72000 72580 ) FS
;
- g4659 INVX1 + PLACED ( 54000 48640 ) N
;
- g4660 INVX1 + PLACED ( 50800 45220 ) FS
;
- g4661 INVX1 + PLACED ( 67200 14440 ) N
;
- g4662 INVX1 + PLACED ( 55200 11020 ) FS
;
- g4663 INVX1 + PLACED ( 46800 14440 ) N
;
- g4664 INVX1 + PLACED ( 43600 24700 ) FS
;
- g4665 INVX1 + PLACED ( 23600 34960 ) N
;
- g4666 INVX1 + PLACED ( 18800 34960 ) N
;
- g4667 INVX1 + PLACED ( 23200 14440 ) N
;
- g4668 INVX1 + PLACED ( 16400 7600 ) N
;
- g4669__6877 AOI222X1 + PLACED ( 54000 38380 ) FS
;
- g4670__2900 AOI222X1 + PLACED ( 49200 38380 ) FS
;
- g4671__2391 AOI222X1 + PLACED ( 58800 11020 ) FS
;
- g4672__7675 AOI222X1 + PLACED ( 51600 11020 ) FS
;
- g4673__7118 AOI222X1 + PLACED ( 45200 11020 ) FS
;
- g4674__8757 AOI222X1 + PLACED ( 40400 21280 ) N
;
- g4675__1786 AOI222X1 + PLACED ( 30000 34960 ) N
;
- g4676__5953 AOI222X1 + PLACED ( 30000 24700 ) FS
;
- g4677__5703 AOI222X1 + PLACED ( 30000 11020 ) FS
;
- g4678__7114 AOI222X1 + PLACED ( 26400 7600 ) N
;
- g4679__5266 MX2XL + PLACED ( 26800 48640 ) N
;
- g4680__2250 AND2X2 + PLACED ( 40400 38380 ) FS
;
- g4681__6083 OAI31X1 + PLACED ( 19200 48640 ) N
;
- g4683__5795 AND3X2 + PLACED ( 42800 41800 ) N
;
- g4684 INVX1 + PLACED ( 31600 48640 ) N
;
- g4685__7344 OR4X1 + PLACED ( 37200 48640 ) N
;
- g4686 INVX1 + PLACED ( 44000 45220 ) FS
;
- g4687__1840 OR4X1 + PLACED ( 48000 45220 ) FS
;
- g4688__5019 NAND4X1 + PLACED ( 70000 48640 ) N
;
- g4689__1857 OR4X1 + PLACED ( 51200 28120 ) N
;
- g4690__9906 OR4X1 + PLACED ( 50800 21280 ) N
;
- g4691__8780 OR4X1 + PLACED ( 51600 45220 ) FS
;
- g4692__4296 OR4X1 + PLACED ( 45200 45220 ) FS
;
- g4693__3772 NOR4XL + PLACED ( 73200 79420 ) FS
;
- g4694__1474 NOR4XL + PLACED ( 80000 48640 ) N
;
- g4695__4547 NOR4XL + PLACED ( 66400 82840 ) N
;
- g4696__9682 NOR4XL + PLACED ( 75600 21280 ) N
;
- g4697__2683 NOR2XL + PLACED ( 40800 48640 ) N
;
- g4698 INVX1 + PLACED ( 20000 45220 ) FS
;
- dec_sub_195_45_g1620__1309 AO21X1 + PLACED ( 28000 21280 ) N
;
- dec_sub_195_45_g1621__6877 NAND2X1 + PLACED ( 73600 76000 ) N
;
- dec_sub_195_45_g1622__2900 NAND2X1 + PLACED ( 44000 21280 ) N
;
- dec_sub_195_45_g1623__2391 NAND2X1 + PLACED ( 54000 28120 ) N
;
- dec_sub_195_45_g1624__7675 NAND2BX1 + PLACED ( 75200 76000 ) N
;
- dec_sub_195_45_g1625__7118 NAND2X1 + PLACED ( 65200 82840 ) N
;
- dec_sub_195_45_g1626__8757 NAND2BX1 + PLACED ( 67200 79420 ) FS
;
- dec_sub_195_45_g1627__1786 NAND2X1 + PLACED ( 53600 17860 ) FS
;
- dec_sub_195_45_g1628__5953 OAI2BB1X1 + PLACED ( 69600 28120 ) N
;
- dec_sub_195_45_g1629__5703 OAI2BB1X1 + PLACED ( 60000 31540 ) FS
;
- dec_sub_195_45_g1630__7114 OAI21XL + PLACED ( 45200 21280 ) N
;
- dec_sub_195_45_g1631__5266 OAI21XL + PLACED ( 57200 31540 ) FS
;
- dec_sub_195_45_g1632__2250 XOR2X1 + PLACED ( 31600 28120 ) N
;
- dec_sub_195_45_g1633 INVX1 + PLACED ( 66400 79420 ) FS
;
- dec_sub_195_45_g1634__6083 ADDHXL + PLACED ( 58400 82840 ) N
;
- dec_sub_195_45_g1635__2703 NAND2BX1 + PLACED ( 21200 24700 ) FS
;
- dec_sub_195_45_g1636__5795 NAND2BX1 + PLACED ( 55200 17860 ) FS
;
- dec_sub_195_45_g1637__7344 NAND2X1 + PLACED ( 73600 17860 ) FS
;
- dec_sub_195_45_g1638__1840 AO21X1 + PLACED ( 78000 79420 ) FS
;
- dec_sub_195_45_g1639__5019 NAND2BX1 + PLACED ( 77600 14440 ) N
;
- dec_sub_195_45_g1640__1857 NOR2XL + PLACED ( 76800 76000 ) N
;
- dec_sub_195_45_g1642__9906 XNOR2X1 + PLACED ( 47200 21280 ) N
;
- dec_sub_195_45_g1643__8780 XNOR2X1 + PLACED ( 52800 34960 ) N
;
- dec_sub_195_45_g1644__4296 XOR2X1 + PLACED ( 27600 17860 ) FS
;
- dec_sub_195_45_g1645 INVX1 + PLACED ( 79200 14440 ) N
;
- dec_sub_195_45_g1646__3772 ADDHXL + PLACED ( 77200 17860 ) FS
;
- dec_sub_195_45_g1647__1474 NAND2BX1 + PLACED ( 78800 41800 ) N
;
- dec_sub_195_45_g1648__4547 NAND2BX1 + PLACED ( 76800 48640 ) N
;
- dec_sub_195_45_g1649__9682 AO21X1 + PLACED ( 38000 28120 ) N
;
- dec_sub_195_45_g1650__2683 OAI2BB1X1 + PLACED ( 60000 28120 ) N
;
- dec_sub_195_45_g1651__1309 OAI2BB1X1 + PLACED ( 70000 14440 ) N
;
- dec_sub_195_45_g1652__6877 AO21X1 + PLACED ( 57600 21280 ) N
;
- dec_sub_195_45_g1653 INVX1 + PLACED ( 76000 41800 ) N
;
- dec_sub_195_45_g1654__2900 ADDHXL + PLACED ( 76000 45220 ) FS
;
- dec_sub_195_45_g1655__2391 OR2X1 + PLACED ( 55200 28120 ) N
;
- dec_sub_195_45_g1656__7675 NAND2BX1 + PLACED ( 53600 21280 ) N
;
- dec_sub_195_45_g1657__7118 NOR2XL + PLACED ( 37600 24700 ) FS
;
- dec_sub_195_45_g1658__8757 NAND2BX1 + PLACED ( 60400 21280 ) N
;
- dec_sub_195_45_g1659__1786 NAND2BX1 + PLACED ( 78400 48640 ) N
;
- dec_sub_195_45_g1660__5953 OAI2BB1X1 + PLACED ( 75600 79420 ) FS
;
- dec_sub_195_45_g1661__5703 OR2X1 + PLACED ( 70400 17860 ) FS
;
- dec_sub_195_45_g1662__7114 NOR2XL + PLACED ( 56400 21280 ) N
;
- dec_sub_195_45_g1663__5266 NOR4XL + PLACED ( 36000 17860 ) FS
;
- dec_sub_195_45_g1664__2250 NAND2X1 + PLACED ( 65200 21280 ) N
;
- dec_sub_195_45_g1665__6083 NAND2X1 + PLACED ( 72400 17860 ) FS
;
- dec_sub_195_45_g1666__2703 OR2X1 + PLACED ( 76000 82840 ) N
;
- dec_sub_195_45_g1667__5795 NAND2X1 + PLACED ( 52400 17860 ) FS
;
- dec_sub_195_45_g1668__7344 AO21X1 + PLACED ( 59600 79420 ) FS
;
- dec_sub_195_45_g1669__1840 NAND2X1 + PLACED ( 55200 24700 ) FS
;
- dec_sub_195_45_g1670__5019 NOR2XL + PLACED ( 65200 79420 ) FS
;
- dec_sub_195_45_g1671__1857 NAND2BX1 + PLACED ( 51600 65740 ) FS
;
- dec_sub_195_45_g1673__9906 AND2X1 + PLACED ( 76800 41800 ) N
;
- dec_sub_195_45_g1674__8780 AO21X1 + PLACED ( 75200 52060 ) FS
;
- dec_sub_195_45_g1675__4296 NAND2BX1 + PLACED ( 51600 69160 ) N
;
- dec_sub_195_45_g1676__3772 NOR2XL + PLACED ( 80000 55480 ) N
;
- dec_sub_195_45_g1677__1474 OAI2BB1X1 + PLACED ( 68800 79420 ) FS
;
- dec_sub_195_45_g1678__4547 NOR3X1 + PLACED ( 78000 52060 ) FS
;
- dec_sub_195_45_g1679 INVX1 + PLACED ( 50000 72580 ) FS
;
- dec_sub_195_45_g1680__9682 ADDHXL + PLACED ( 49600 76000 ) N
;
- dec_sub_195_45_g1681__2683 OR2X1 + PLACED ( 70000 82840 ) N
;
- dec_sub_195_45_g1682__1309 OR2X1 + PLACED ( 71200 79420 ) FS
;
- dec_sub_195_45_g1683__6877 NAND2X1 + PLACED ( 58800 72580 ) FS
;
- dec_sub_195_45_g1684__2900 NAND2X1 + PLACED ( 68800 82840 ) N
;
- dec_sub_195_45_g1685__2391 NAND2BX1 + PLACED ( 56800 82840 ) N
;
- dec_sub_195_45_g1686__7675 NAND2BX1 + PLACED ( 58000 79420 ) FS
;
- dec_sub_195_45_g1687__7118 AND2X1 + PLACED ( 52000 72580 ) FS
;
- dec_sub_195_45_g1688__8757 NOR4BBX1 + PLACED ( 51600 24700 ) FS
;
- dec_sub_195_45_g1689__1786 AND3XL + PLACED ( 57200 28120 ) N
;
- dec_sub_195_45_g1690__5953 AND2X1 + PLACED ( 71200 21280 ) N
;
- dec_sub_195_45_g1691__5703 AO21X1 + PLACED ( 47600 65740 ) FS
;
- dec_sub_195_45_g1692__7114 OR4X1 + PLACED ( 73200 82840 ) N
;
- dec_sub_195_45_g1695__2250 NOR2XL + PLACED ( 80400 41800 ) N
;
- dec_sub_195_45_g1696__6083 NOR2XL + PLACED ( 55200 21280 ) N
;
- dec_sub_195_45_g1697__2703 NOR2XL + PLACED ( 48400 69160 ) N
;
- dec_sub_195_45_g1698__5795 NOR2XL + PLACED ( 56400 24700 ) FS
;
- dec_sub_195_45_g1699__7344 NOR2XL + PLACED ( 65200 31540 ) FS
;
- dec_sub_195_45_g1700__1840 NOR2XL + PLACED ( 73200 21280 ) N
;
- dec_sub_195_45_g1701__5019 NOR2XL + PLACED ( 50800 72580 ) FS
;
- dec_sub_195_45_g1702__1857 NOR2XL + PLACED ( 75600 17860 ) FS
;
- dec_sub_195_45_g2__9906 NAND2BX1 + PLACED ( 74400 34960 ) N
;
- g2 NOR2BX1 + PLACED ( 40400 45220 ) FS
;
- reg_ctrl_reg\[3\] DFFRX2 + PLACED ( 34000 52060 ) FS
;
- reg_ctrl_reg\[2\] DFFRX2 + PLACED ( 34000 72580 ) FS
;
- reg_curr_val_reg\[0\] SDFFRXL + PLACED ( 28400 45220 ) FS
;
- reg_curr_val_reg\[6\] SDFFRXL + PLACED ( 54800 89680 ) N
;
- reg_curr_val_reg\[16\] SDFFRXL + PLACED ( 88800 17860 ) FS
;
- reg_curr_val_reg\[14\] SDFFRXL + PLACED ( 88800 41800 ) N
;
- reg_curr_val_reg\[2\] SDFFRXL + PLACED ( 44000 79420 ) FS
;
- g4734 AO21X1 + PLACED ( 65200 34960 ) N
;
- g4735 AO21X1 + PLACED ( 50000 31540 ) FS
;
- g4736 AO21X1 + PLACED ( 88800 72580 ) FS
;
- g4737 AO21X1 + PLACED ( 83600 79420 ) FS
;
- g4738 AO21X1 + PLACED ( 80800 79420 ) FS
;
- g4739 AO21X1 + PLACED ( 37600 21280 ) N
;
- g4740 AO21X1 + PLACED ( 58800 41800 ) N
;
- g4741 AO21X1 + PLACED ( 38000 11020 ) FS
;
- g4742 AO21X1 + PLACED ( 38000 7600 ) N
;
- g4743 AO21X1 + PLACED ( 36000 31540 ) FS
;
- g4744 AO21X1 + PLACED ( 68000 34960 ) N
;
- g4745 AO21X1 + PLACED ( 83600 24700 ) FS
;
- g4746 AO21X1 + PLACED ( 45600 24700 ) FS
;
- g4747 AO21X1 + PLACED ( 82400 14440 ) N
;
- g4748 AO21X1 + PLACED ( 48800 24700 ) FS
;
- g4749 AO21X1 + PLACED ( 85200 14440 ) N
;
- g4750 AO21X1 + PLACED ( 84800 21280 ) N
;
- g4751 AO21X1 + PLACED ( 81600 45220 ) FS
;
- g4752 AO21X1 + PLACED ( 56000 11020 ) FS
;
- g4753 AO21X1 + PLACED ( 82800 52060 ) FS
;
- g4754 AO21X1 + PLACED ( 81200 55480 ) N
;
- g4755 AO21X1 + PLACED ( 65200 11020 ) FS
;
- g4756 AO21X1 + PLACED ( 79200 62320 ) N
;
- g4757 AO21X1 + PLACED ( 84400 69160 ) N
;
- g4758 OAI221X1 + PLACED ( 36000 76000 ) N
;
- g4759 OR4X1 + PLACED ( 10800 28120 ) N
;
- g4760 OR4X1 + PLACED ( 10000 24700 ) FS
;
- g4761 NOR4XL + PLACED ( 67200 86260 ) FS
;
END COMPONENTS
PINS 88 ;
- PCLK + NET PCLK + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 580 )
+ FIXED ( 63400 114380 ) S ;
- PCLKG + NET PCLKG + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 580 )
+ FIXED ( 65400 114380 ) S ;
- PRESETn + NET PRESETn + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 2090 ) E ;
- PSEL + NET PSEL + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 4370 ) E ;
- PADDR[11] + NET PADDR[11] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 27170 ) E ;
- PADDR[10] + NET PADDR[10] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 24890 ) E ;
- PADDR[9] + NET PADDR[9] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 22610 ) E ;
- PADDR[8] + NET PADDR[8] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 20330 ) E ;
- PADDR[7] + NET PADDR[7] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 18050 ) E ;
- PADDR[6] + NET PADDR[6] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 15770 ) E ;
- PADDR[5] + NET PADDR[5] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 13490 ) E ;
- PADDR[4] + NET PADDR[4] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 11210 ) E ;
- PADDR[3] + NET PADDR[3] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 8930 ) E ;
- PADDR[2] + NET PADDR[2] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 6650 ) E ;
- PENABLE + NET PENABLE + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 29450 ) E ;
- PWRITE + NET PWRITE + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 31730 ) E ;
- PWDATA[31] + NET PWDATA[31] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 27000 0 ) N ;
- PWDATA[30] + NET PWDATA[30] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 29400 0 ) N ;
- PWDATA[29] + NET PWDATA[29] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 31800 0 ) N ;
- PWDATA[28] + NET PWDATA[28] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 34200 0 ) N ;
- PWDATA[27] + NET PWDATA[27] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 36600 0 ) N ;
- PWDATA[26] + NET PWDATA[26] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 39000 0 ) N ;
- PWDATA[25] + NET PWDATA[25] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 41400 0 ) N ;
- PWDATA[24] + NET PWDATA[24] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 43800 0 ) N ;
- PWDATA[23] + NET PWDATA[23] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 46200 0 ) N ;
- PWDATA[22] + NET PWDATA[22] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 48600 0 ) N ;
- PWDATA[21] + NET PWDATA[21] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 51000 0 ) N ;
- PWDATA[20] + NET PWDATA[20] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 53400 0 ) N ;
- PWDATA[19] + NET PWDATA[19] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 55800 0 ) N ;
- PWDATA[18] + NET PWDATA[18] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 58200 0 ) N ;
- PWDATA[17] + NET PWDATA[17] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 60600 0 ) N ;
- PWDATA[16] + NET PWDATA[16] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 63000 0 ) N ;
- PWDATA[15] + NET PWDATA[15] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 65400 0 ) N ;
- PWDATA[14] + NET PWDATA[14] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 67800 0 ) N ;
- PWDATA[13] + NET PWDATA[13] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 70200 0 ) N ;
- PWDATA[12] + NET PWDATA[12] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 72600 0 ) N ;
- PWDATA[11] + NET PWDATA[11] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 75000 0 ) N ;
- PWDATA[10] + NET PWDATA[10] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 77400 0 ) N ;
- PWDATA[9] + NET PWDATA[9] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 79800 0 ) N ;
- PWDATA[8] + NET PWDATA[8] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 82200 0 ) N ;
- PWDATA[7] + NET PWDATA[7] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 84600 0 ) N ;
- PWDATA[6] + NET PWDATA[6] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 87000 0 ) N ;
- PWDATA[5] + NET PWDATA[5] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 89400 0 ) N ;
- PWDATA[4] + NET PWDATA[4] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 91800 0 ) N ;
- PWDATA[3] + NET PWDATA[3] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 94200 0 ) N ;
- PWDATA[2] + NET PWDATA[2] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 96600 0 ) N ;
- PWDATA[1] + NET PWDATA[1] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 99000 0 ) N ;
- PWDATA[0] + NET PWDATA[0] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 670 )
+ FIXED ( 101400 0 ) N ;
- ECOREVNUM[3] + NET ECOREVNUM[3] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 112290 ) E ;
- ECOREVNUM[2] + NET ECOREVNUM[2] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 111530 ) E ;
- ECOREVNUM[1] + NET ECOREVNUM[1] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 109250 ) E ;
- ECOREVNUM[0] + NET ECOREVNUM[0] + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 0 106970 ) E ;
- PRDATA[31] + NET PRDATA[31] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 25650 ) W ;
- PRDATA[30] + NET PRDATA[30] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 27930 ) W ;
- PRDATA[29] + NET PRDATA[29] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 30210 ) W ;
- PRDATA[28] + NET PRDATA[28] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 32490 ) W ;
- PRDATA[27] + NET PRDATA[27] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 34770 ) W ;
- PRDATA[26] + NET PRDATA[26] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 37050 ) W ;
- PRDATA[25] + NET PRDATA[25] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 39330 ) W ;
- PRDATA[24] + NET PRDATA[24] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 41610 ) W ;
- PRDATA[23] + NET PRDATA[23] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 43890 ) W ;
- PRDATA[22] + NET PRDATA[22] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 46170 ) W ;
- PRDATA[21] + NET PRDATA[21] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 48450 ) W ;
- PRDATA[20] + NET PRDATA[20] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 50730 ) W ;
- PRDATA[19] + NET PRDATA[19] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 53010 ) W ;
- PRDATA[18] + NET PRDATA[18] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 55290 ) W ;
- PRDATA[17] + NET PRDATA[17] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 57570 ) W ;
- PRDATA[16] + NET PRDATA[16] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 59850 ) W ;
- PRDATA[15] + NET PRDATA[15] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 62130 ) W ;
- PRDATA[14] + NET PRDATA[14] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 64410 ) W ;
- PRDATA[13] + NET PRDATA[13] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 66690 ) W ;
- PRDATA[12] + NET PRDATA[12] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 68970 ) W ;
- PRDATA[11] + NET PRDATA[11] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 71250 ) W ;
- PRDATA[10] + NET PRDATA[10] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 73530 ) W ;
- PRDATA[9] + NET PRDATA[9] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 75810 ) W ;
- PRDATA[8] + NET PRDATA[8] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 78090 ) W ;
- PRDATA[7] + NET PRDATA[7] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 80370 ) W ;
- PRDATA[6] + NET PRDATA[6] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 82650 ) W ;
- PRDATA[5] + NET PRDATA[5] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 84930 ) W ;
- PRDATA[4] + NET PRDATA[4] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 87210 ) W ;
- PRDATA[3] + NET PRDATA[3] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 89490 ) W ;
- PRDATA[2] + NET PRDATA[2] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 91770 ) W ;
- PRDATA[1] + NET PRDATA[1] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 94050 ) W ;
- PRDATA[0] + NET PRDATA[0] + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 96330 ) W ;
- PREADY + NET PREADY + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 23370 ) W ;
- PSLVERR + NET PSLVERR + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 21090 ) W ;
- EXTIN + NET EXTIN + DIRECTION INPUT + USE SIGNAL
+ LAYER Metal2 ( -70 0 ) ( 70 580 )
+ FIXED ( 61400 114380 ) S ;
- TIMERINT + NET TIMERINT + DIRECTION OUTPUT + USE SIGNAL
+ LAYER Metal3 ( -70 0 ) ( 70 580 )
+ FIXED ( 127600 18810 ) W ;
END PINS
SPECIALNETS 2 ;
- VDD
+ ROUTED Metal1 240 + SHAPE COREWIRE ( 123600 106780 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 99940 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 93100 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 86260 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 79420 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 72580 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 65740 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 58900 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 106780 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 99940 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 93100 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 86260 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 79420 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 72580 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 65740 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 58900 ) ( 4000 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 106780 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 99940 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 93100 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 86260 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 79420 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 72580 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 65740 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 58900 ) ( 123600 * )
NEW Metal1 1000 + SHAPE RING ( 2000 111700 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 52060 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 45220 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 38380 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 31540 ) ( 125600 * )
NEW Metal1 120 + SHAPE COREWIRE ( 123600 4240 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 24700 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 17860 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 11020 ) ( 125600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 52060 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 45220 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 38380 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 31540 ) ( 4000 * )
NEW Metal1 120 + SHAPE COREWIRE ( 2000 4240 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 11020 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 24700 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 2000 17860 ) ( 4000 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 52060 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 45220 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 38380 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 31540 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 24700 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 17860 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 11020 ) ( 123600 * )
NEW Metal1 120 + SHAPE FOLLOWPIN ( 4000 4240 ) ( 123600 * )
NEW Metal1 1000 + SHAPE RING ( 2000 2680 ) ( 125600 * )
NEW Metal2 1000 + SHAPE RING ( 2500 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE RING ( 125100 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE STRIPE ( 4500 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE STRIPE ( 33670 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE STRIPE ( 62840 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE STRIPE ( 92010 2180 ) ( * 112200 )
NEW Metal2 1000 + SHAPE STRIPE ( 121180 2180 ) ( * 112200 )
NEW Metal2 0 + SHAPE RING ( 125100 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 92010 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 121180 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 125100 106780 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 99940 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 93100 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 86260 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 79420 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 72580 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 65740 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 58900 ) M2_M1_3
NEW Metal2 0 + SHAPE STRIPE ( 33670 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 4500 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE RING ( 2500 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 62840 111700 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 2500 106780 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 99940 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 93100 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 86260 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 79420 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 72580 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 65740 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 58900 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 52060 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 45220 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 38380 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 31540 ) M2_M1_3
NEW Metal2 0 + SHAPE RING ( 125100 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 92010 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 121180 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 125100 4240 ) M2_M1_2
NEW Metal2 0 + SHAPE COREWIRE ( 125100 24700 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 17860 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 125100 11020 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 52060 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 45220 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 38380 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 31540 ) M2_M1_3
NEW Metal2 0 + SHAPE STRIPE ( 33670 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 4500 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE RING ( 2500 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 62840 2680 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 2500 4240 ) M2_M1_2
NEW Metal2 0 + SHAPE COREWIRE ( 2500 11020 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 24700 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 2500 17860 ) M2_M1_3
+ USE POWER
;
- VSS
+ ROUTED Metal1 1000 + SHAPE RING ( 122580 112900 ) ( 126900 * )
NEW Metal1 1000 + SHAPE RING ( 93410 112900 ) ( 123580 * )
NEW Metal1 1000 + SHAPE RING ( 64240 112900 ) ( 94410 * )
NEW Metal1 120 + SHAPE COREWIRE ( 123600 110140 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 103360 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 89680 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 96520 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 82840 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 76000 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 69160 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 62320 ) ( 126900 * )
NEW Metal1 1000 + SHAPE RING ( 5900 112900 ) ( 36070 * )
NEW Metal1 1000 + SHAPE RING ( 700 112900 ) ( 6900 * )
NEW Metal1 120 + SHAPE COREWIRE ( 700 110140 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 103360 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 89680 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 96520 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 82840 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 76000 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 69160 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 62320 ) ( 4000 * )
NEW Metal1 1000 + SHAPE RING ( 35070 112900 ) ( 65240 * )
NEW Metal1 120 + SHAPE FOLLOWPIN ( 4000 110140 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 103360 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 96520 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 89680 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 82840 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 76000 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 69160 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 62320 ) ( 123600 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 55480 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 48640 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 41800 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 34960 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 28120 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 7600 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 14440 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 123600 21280 ) ( 126900 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 28120 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 34960 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 41800 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 48640 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 55480 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 7600 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 14440 ) ( 4000 * )
NEW Metal1 240 + SHAPE COREWIRE ( 700 21280 ) ( 4000 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 55480 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 48640 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 41800 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 34960 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 28120 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 21280 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 14440 ) ( 123600 * )
NEW Metal1 240 + SHAPE FOLLOWPIN ( 4000 7600 ) ( 123600 * )
NEW Metal1 1000 + SHAPE RING ( 700 1480 ) ( 126900 * )
NEW Metal2 1000 + SHAPE RING ( 1200 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE RING ( 126400 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE STRIPE ( 6400 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE STRIPE ( 35570 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE STRIPE ( 64740 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE STRIPE ( 93910 980 ) ( * 113400 )
NEW Metal2 1000 + SHAPE STRIPE ( 123080 980 ) ( * 113400 )
NEW Metal2 0 + SHAPE COREWIRE ( 126400 96520 ) M2_M1_3
NEW Metal2 0 + SHAPE RING ( 126400 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 64740 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 93910 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 123080 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 126400 110140 ) M2_M1_2
NEW Metal2 0 + SHAPE COREWIRE ( 126400 103360 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 89680 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 82840 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 76000 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 69160 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 62320 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 96520 ) M2_M1_3
NEW Metal2 0 + SHAPE RING ( 1200 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 6400 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 35570 112900 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 1200 110140 ) M2_M1_2
NEW Metal2 0 + SHAPE COREWIRE ( 1200 103360 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 89680 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 82840 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 76000 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 69160 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 62320 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 55480 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 48640 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 41800 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 34960 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 28120 ) M2_M1_3
NEW Metal2 0 + SHAPE RING ( 126400 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 64740 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 93910 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 123080 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE COREWIRE ( 126400 7600 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 14440 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 126400 21280 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 28120 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 55480 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 34960 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 41800 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 48640 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 7600 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 14440 ) M2_M1_3
NEW Metal2 0 + SHAPE COREWIRE ( 1200 21280 ) M2_M1_3
NEW Metal2 0 + SHAPE RING ( 1200 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 6400 1480 ) M2_M1_1
NEW Metal2 0 + SHAPE STRIPE ( 35570 1480 ) M2_M1_1
+ USE GROUND
;
END SPECIALNETS
NETS 576 ;
- FE_OFN182_PRDATA_25
( FE_OFC181_PRDATA_25 Y ) ( FE_OFC182_PRDATA_25 A )
;
- FE_OFN181_PRDATA_25
( FE_OFC90_PRDATA_25 Y ) ( FE_OFC181_PRDATA_25 A )
;
- FE_OFN180_PRDATA_2
( FE_OFC179_PRDATA_2 Y ) ( FE_OFC180_PRDATA_2 A )
;
- FE_OFN179_PRDATA_2
( FE_OFC94_PRDATA_2 Y ) ( FE_OFC179_PRDATA_2 A )
;
- FE_OFN178_PRDATA_5
( FE_OFC177_PRDATA_5 Y ) ( FE_OFC178_PRDATA_5 A )
;
- FE_OFN177_PRDATA_5
( FE_OFC98_PRDATA_5 Y ) ( FE_OFC177_PRDATA_5 A )
;
- FE_OFN176_PRDATA_22
( FE_OFC175_PRDATA_22 Y ) ( FE_OFC176_PRDATA_22 A )
;
- FE_OFN175_PRDATA_22
( FE_OFC96_PRDATA_22 Y ) ( FE_OFC175_PRDATA_22 A )
;
- FE_OFN174_PRDATA_31
( FE_OFC173_PRDATA_31 Y ) ( FE_OFC174_PRDATA_31 A )
;
- FE_OFN173_PRDATA_31
( FE_OFC88_PRDATA_31 Y ) ( FE_OFC173_PRDATA_31 A )
;
- FE_OFN172_PRDATA_8
( FE_OFC171_PRDATA_8 Y ) ( FE_OFC172_PRDATA_8 A )
;
- FE_OFN171_PRDATA_8
( FE_OFC104_PRDATA_8 Y ) ( FE_OFC171_PRDATA_8 A )
;
- FE_OFN170_PRDATA_6
( FE_OFC169_PRDATA_6 Y ) ( FE_OFC170_PRDATA_6 A )
;
- FE_OFN169_PRDATA_6
( FE_OFC102_PRDATA_6 Y ) ( FE_OFC169_PRDATA_6 A )
;
- FE_OFN168_PRDATA_19
( FE_OFC167_PRDATA_19 Y ) ( FE_OFC168_PRDATA_19 A )
;
- FE_OFN167_PRDATA_19
( FE_OFC92_PRDATA_19 Y ) ( FE_OFC167_PRDATA_19 A )
;
- FE_OFN166_PRDATA_3
( FE_OFC165_PRDATA_3 Y ) ( FE_OFC166_PRDATA_3 A )
;
- FE_OFN165_PRDATA_3
( FE_OFC100_PRDATA_3 Y ) ( FE_OFC165_PRDATA_3 A )
;
- FE_OFN164_PRDATA_4
( FE_OFC163_PRDATA_4 Y ) ( FE_OFC164_PRDATA_4 A )
;
- FE_OFN163_PRDATA_4
( FE_OFC110_PRDATA_4 Y ) ( FE_OFC163_PRDATA_4 A )
;
- FE_OFN162_PRDATA_9
( FE_OFC161_PRDATA_9 Y ) ( FE_OFC162_PRDATA_9 A )
;
- FE_OFN161_PRDATA_9
( FE_OFC134_PRDATA_9 Y ) ( FE_OFC161_PRDATA_9 A )
;
- FE_OFN160_PRDATA_13
( FE_OFC159_PRDATA_13 Y ) ( FE_OFC160_PRDATA_13 A )
;
- FE_OFN159_PRDATA_13
( FE_OFC130_PRDATA_13 Y ) ( FE_OFC159_PRDATA_13 A )
;
- FE_OFN158_PRDATA_18
( FE_OFC157_PRDATA_18 Y ) ( FE_OFC158_PRDATA_18 A )
;
- FE_OFN157_PRDATA_18
( FE_OFC114_PRDATA_18 Y ) ( FE_OFC157_PRDATA_18 A )
;
- FE_OFN156_PRDATA_21
( FE_OFC155_PRDATA_21 Y ) ( FE_OFC156_PRDATA_21 A )
;
- FE_OFN155_PRDATA_21
( FE_OFC124_PRDATA_21 Y ) ( FE_OFC155_PRDATA_21 A )
;
- FE_OFN154_PRDATA_7
( FE_OFC153_PRDATA_7 Y ) ( FE_OFC154_PRDATA_7 A )
;
- FE_OFN153_PRDATA_7
( FE_OFC122_PRDATA_7 Y ) ( FE_OFC153_PRDATA_7 A )
;
- FE_OFN152_PRDATA_15
( FE_OFC151_PRDATA_15 Y ) ( FE_OFC152_PRDATA_15 A )
;
- FE_OFN151_PRDATA_15
( FE_OFC120_PRDATA_15 Y ) ( FE_OFC151_PRDATA_15 A )
;
- FE_OFN150_PRDATA_16
( FE_OFC149_PRDATA_16 Y ) ( FE_OFC150_PRDATA_16 A )
;
- FE_OFN149_PRDATA_16
( FE_OFC126_PRDATA_16 Y ) ( FE_OFC149_PRDATA_16 A )
;
- FE_OFN148_PRDATA_24
( FE_OFC147_PRDATA_24 Y ) ( FE_OFC148_PRDATA_24 A )
;
- FE_OFN147_PRDATA_24
( FE_OFC106_PRDATA_24 Y ) ( FE_OFC147_PRDATA_24 A )
;
- FE_OFN146_PRDATA_28
( FE_OFC145_PRDATA_28 Y ) ( FE_OFC146_PRDATA_28 A )
;
- FE_OFN145_PRDATA_28
( FE_OFC116_PRDATA_28 Y ) ( FE_OFC145_PRDATA_28 A )
;
- FE_OFN144_PRDATA_30
( FE_OFC143_PRDATA_30 Y ) ( FE_OFC144_PRDATA_30 A )
;
- FE_OFN143_PRDATA_30
( FE_OFC108_PRDATA_30 Y ) ( FE_OFC143_PRDATA_30 A )
;
- FE_OFN142_PRDATA_11
( FE_OFC141_PRDATA_11 Y ) ( FE_OFC142_PRDATA_11 A )
;
- FE_OFN141_PRDATA_11
( FE_OFC132_PRDATA_11 Y ) ( FE_OFC141_PRDATA_11 A )
;
- FE_OFN140_PRDATA_14
( FE_OFC139_PRDATA_14 Y ) ( FE_OFC140_PRDATA_14 A )
;
- FE_OFN139_PRDATA_14
( FE_OFC128_PRDATA_14 Y ) ( FE_OFC139_PRDATA_14 A )
;
- FE_OFN138_PRDATA_26
( FE_OFC137_PRDATA_26 Y ) ( FE_OFC138_PRDATA_26 A )
;
- FE_OFN137_PRDATA_26
( FE_OFC118_PRDATA_26 Y ) ( FE_OFC137_PRDATA_26 A )
;
- FE_OFN136_PRDATA_29
( FE_OFC135_PRDATA_29 Y ) ( FE_OFC136_PRDATA_29 A )
;
- FE_OFN135_PRDATA_29
( FE_OFC112_PRDATA_29 Y ) ( FE_OFC135_PRDATA_29 A )
;
- FE_OFN134_PRDATA_9
( FE_OFC133_PRDATA_9 Y ) ( FE_OFC134_PRDATA_9 A )
;
- FE_OFN132_PRDATA_11
( FE_OFC131_PRDATA_11 Y ) ( FE_OFC132_PRDATA_11 A )
;
- FE_OFN130_PRDATA_13
( FE_OFC129_PRDATA_13 Y ) ( FE_OFC130_PRDATA_13 A )
;
- FE_OFN128_PRDATA_14
( FE_OFC127_PRDATA_14 Y ) ( FE_OFC128_PRDATA_14 A )
;
- FE_OFN126_PRDATA_16
( FE_OFC125_PRDATA_16 Y ) ( FE_OFC126_PRDATA_16 A )
;
- FE_OFN124_PRDATA_21
( FE_OFC123_PRDATA_21 Y ) ( FE_OFC124_PRDATA_21 A )
;
- FE_OFN122_PRDATA_7
( FE_OFC121_PRDATA_7 Y ) ( FE_OFC122_PRDATA_7 A )
;
- FE_OFN120_PRDATA_15
( FE_OFC119_PRDATA_15 Y ) ( FE_OFC120_PRDATA_15 A )
;
- FE_OFN118_PRDATA_26
( FE_OFC117_PRDATA_26 Y ) ( FE_OFC118_PRDATA_26 A )
;
- FE_OFN116_PRDATA_28
( FE_OFC115_PRDATA_28 Y ) ( FE_OFC116_PRDATA_28 A )
;
- FE_OFN114_PRDATA_18
( FE_OFC113_PRDATA_18 Y ) ( FE_OFC114_PRDATA_18 A )
;
- FE_OFN112_PRDATA_29
( FE_OFC111_PRDATA_29 Y ) ( FE_OFC112_PRDATA_29 A )
;
- FE_OFN110_PRDATA_4
( FE_OFC109_PRDATA_4 Y ) ( FE_OFC110_PRDATA_4 A )
;
- FE_OFN108_PRDATA_30
( FE_OFC107_PRDATA_30 Y ) ( FE_OFC108_PRDATA_30 A )
;
- FE_OFN106_PRDATA_24
( FE_OFC105_PRDATA_24 Y ) ( FE_OFC106_PRDATA_24 A )
;
- FE_OFN104_PRDATA_8
( FE_OFC103_PRDATA_8 Y ) ( FE_OFC104_PRDATA_8 A )
;
- FE_OFN102_PRDATA_6
( FE_OFC101_PRDATA_6 Y ) ( FE_OFC102_PRDATA_6 A )
;
- FE_OFN100_PRDATA_3
( FE_OFC99_PRDATA_3 Y ) ( FE_OFC100_PRDATA_3 A )
;
- FE_OFN98_PRDATA_5
( FE_OFC97_PRDATA_5 Y ) ( FE_OFC98_PRDATA_5 A )
;
- FE_OFN96_PRDATA_22
( FE_OFC95_PRDATA_22 Y ) ( FE_OFC96_PRDATA_22 A )
;
- FE_OFN94_PRDATA_2
( FE_OFC93_PRDATA_2 Y ) ( FE_OFC94_PRDATA_2 A )
;
- FE_OFN92_PRDATA_19
( FE_OFC91_PRDATA_19 Y ) ( FE_OFC92_PRDATA_19 A )
;
- FE_OFN90_PRDATA_25
( FE_OFC89_PRDATA_25 Y ) ( FE_OFC90_PRDATA_25 A )
;
- FE_OFN88_PRDATA_31
( FE_OFC87_PRDATA_31 Y ) ( FE_OFC88_PRDATA_31 A )
;
- FE_OFN86_PRDATA_12
( FE_OFC85_PRDATA_12 Y ) ( FE_OFC86_PRDATA_12 A )
;
- FE_OFN84_PRDATA_10
( FE_OFC83_PRDATA_10 Y ) ( FE_OFC84_PRDATA_10 A )
;
- FE_OFN82_PRDATA_20
( FE_OFC81_PRDATA_20 Y ) ( FE_OFC82_PRDATA_20 A )
;
- FE_OFN80_PRDATA_17
( FE_OFC79_PRDATA_17 Y ) ( FE_OFC80_PRDATA_17 A )
;
- FE_OFN78_PRDATA_0
( FE_OFC77_PRDATA_0 Y ) ( FE_OFC78_PRDATA_0 A )
;
- FE_OFN76_PRDATA_23
( FE_OFC75_PRDATA_23 Y ) ( FE_OFC76_PRDATA_23 A )
;
- FE_OFN74_PRDATA_27
( FE_OFC73_PRDATA_27 Y ) ( FE_OFC74_PRDATA_27 A )
;
- FE_OFN72_PRDATA_1
( FE_OFC71_PRDATA_1 Y ) ( FE_OFC72_PRDATA_1 A )
;
- FE_OFN70_TIMERINT
( FE_OFC69_TIMERINT Y ) ( FE_OFC70_TIMERINT A )
;
- FE_OFN69_TIMERINT
( FE_OFC68_TIMERINT Y ) ( FE_OFC69_TIMERINT A )
;
- FE_OFN68_TIMERINT
( FE_OFC67_TIMERINT Y ) ( FE_OFC68_TIMERINT A )
;
- FE_OFN67_TIMERINT
( g4679__5266 A ) ( FE_OFC11_TIMERINT Y ) ( FE_OFC67_TIMERINT A )
;
- FE_OFN34_PRDATA_8
( g4738 Y ) ( FE_OFC103_PRDATA_8 A )
;
- FE_OFN33_PRDATA_9
( g4737 Y ) ( FE_OFC133_PRDATA_9 A )
;
- FE_OFN32_PRDATA_10
( g4736 Y ) ( FE_OFC83_PRDATA_10 A )
;
- FE_OFN31_PRDATA_11
( g4757 Y ) ( FE_OFC131_PRDATA_11 A )
;
- FE_OFN30_PRDATA_12
( g4756 Y ) ( FE_OFC85_PRDATA_12 A )
;
- FE_OFN29_PRDATA_13
( g4754 Y ) ( FE_OFC129_PRDATA_13 A )
;
- FE_OFN28_PRDATA_14
( g4753 Y ) ( FE_OFC127_PRDATA_14 A )
;
- FE_OFN27_PRDATA_15
( g4751 Y ) ( FE_OFC119_PRDATA_15 A )
;
- FE_OFN26_PRDATA_16
( g4750 Y ) ( FE_OFC125_PRDATA_16 A )
;
- FE_OFN25_PRDATA_17
( g4749 Y ) ( FE_OFC79_PRDATA_17 A )
;
- FE_OFN24_PRDATA_18
( g4747 Y ) ( FE_OFC113_PRDATA_18 A )
;
- FE_OFN23_PRDATA_19
( g4745 Y ) ( FE_OFC91_PRDATA_19 A )
;
- FE_OFN22_PRDATA_20
( g4744 Y ) ( FE_OFC81_PRDATA_20 A )
;
- FE_OFN21_PRDATA_21
( g4734 Y ) ( FE_OFC123_PRDATA_21 A )
;
- FE_OFN20_PRDATA_22
( g4740 Y ) ( FE_OFC95_PRDATA_22 A )
;
- FE_OFN19_PRDATA_23
( g4735 Y ) ( FE_OFC75_PRDATA_23 A )
;
- FE_OFN18_PRDATA_24
( g4755 Y ) ( FE_OFC105_PRDATA_24 A )
;
- FE_OFN17_PRDATA_25
( g4752 Y ) ( FE_OFC89_PRDATA_25 A )
;
- FE_OFN16_PRDATA_26
( g4748 Y ) ( FE_OFC117_PRDATA_26 A )
;
- FE_OFN15_PRDATA_27
( g4746 Y ) ( FE_OFC73_PRDATA_27 A )
;
- FE_OFN14_PRDATA_28
( g4743 Y ) ( FE_OFC115_PRDATA_28 A )
;
- FE_OFN13_PRDATA_29
( g4739 Y ) ( FE_OFC111_PRDATA_29 A )
;
- FE_OFN12_PRDATA_30
( g4741 Y ) ( FE_OFC107_PRDATA_30 A )
;
- FE_OFN11_TIMERINT
( FE_OFC10_TIMERINT Y ) ( FE_OFC11_TIMERINT A )
;
- FE_OFN10_TIMERINT
( reg_timer_int_reg Q ) ( g4434__5019 B0 ) ( FE_OFC10_TIMERINT A )
;
- FE_OFN9_PRDATA_0
( g4404__1474 Y ) ( FE_OFC77_PRDATA_0 A )
;
- FE_OFN8_PRDATA_1
( g4412__7675 Y ) ( FE_OFC71_PRDATA_1 A )
;
- FE_OFN7_PRDATA_2
( g4409__6877 Y ) ( FE_OFC93_PRDATA_2 A )
;
- FE_OFN6_PRDATA_3
( g4403__3772 Y ) ( FE_OFC99_PRDATA_3 A )
;
- FE_OFN5_PRDATA_4
( g4402__4296 Y ) ( FE_OFC109_PRDATA_4 A )
;
- FE_OFN4_PRDATA_5
( g4401__8780 Y ) ( FE_OFC97_PRDATA_5 A )
;
- FE_OFN3_PRDATA_6
( g4411__2391 Y ) ( FE_OFC101_PRDATA_6 A )
;
- FE_OFN2_PRDATA_7
( g4410__2900 Y ) ( FE_OFC121_PRDATA_7 A )
;
- FE_OFN1_PRDATA_31
( g4742 Y ) ( FE_OFC87_PRDATA_31 A )
;
- FE_OFN0_PRESETn
( reg_curr_val_reg\[2\] RN ) ( reg_curr_val_reg\[6\] RN )
( reg_curr_val_reg\[0\] RN ) ( reg_ctrl_reg\[2\] RN ) ( reg_ctrl_reg\[3\] RN )
( reg_timer_int_reg RN ) ( reg_curr_val_reg\[31\] RN )
( reg_curr_val_reg\[30\] RN ) ( reg_curr_val_reg\[29\] RN )
( reg_curr_val_reg\[28\] RN ) ( reg_curr_val_reg\[23\] RN )
( reg_curr_val_reg\[22\] RN ) ( reg_curr_val_reg\[21\] RN )
( reg_curr_val_reg\[12\] RN ) ( reg_curr_val_reg\[11\] RN )
( reg_curr_val_reg\[10\] RN ) ( reg_curr_val_reg\[9\] RN )
( reg_curr_val_reg\[8\] RN ) ( reg_curr_val_reg\[7\] RN )
( reg_curr_val_reg\[5\] RN ) ( reg_curr_val_reg\[4\] RN )
( reg_curr_val_reg\[3\] RN ) ( reg_curr_val_reg\[1\] RN )
( reg_reload_val_reg\[29\] RN ) ( reg_reload_val_reg\[28\] RN )
( reg_reload_val_reg\[22\] RN ) ( reg_reload_val_reg\[12\] RN )
( reg_reload_val_reg\[11\] RN ) ( reg_reload_val_reg\[10\] RN )
( reg_reload_val_reg\[9\] RN ) ( reg_reload_val_reg\[8\] RN )
( reg_reload_val_reg\[7\] RN ) ( reg_reload_val_reg\[6\] RN )
( reg_reload_val_reg\[5\] RN ) ( reg_reload_val_reg\[4\] RN )
( reg_reload_val_reg\[3\] RN ) ( reg_reload_val_reg\[2\] RN )
( reg_reload_val_reg\[1\] RN ) ( reg_reload_val_reg\[0\] RN )
( reg_ctrl_reg\[1\] RN ) ( reg_ctrl_reg\[0\] RN )
( read_mux_byte0_reg_reg\[7\] RN ) ( read_mux_byte0_reg_reg\[6\] RN )
( read_mux_byte0_reg_reg\[5\] RN ) ( read_mux_byte0_reg_reg\[4\] RN )
( read_mux_byte0_reg_reg\[3\] RN ) ( read_mux_byte0_reg_reg\[2\] RN )
( read_mux_byte0_reg_reg\[1\] RN ) ( read_mux_byte0_reg_reg\[0\] RN )
( ext_in_sync2_reg RN ) ( ext_in_sync1_reg RN ) ( ext_in_delay_reg RN )
( FE_OFC0_PRESETn Y )
;
- PCLK
( PIN PCLK ) ( reg_timer_int_reg CK ) ( RC_CG_HIER_INST1/RC_CGIC_INST CK )
( RC_CG_HIER_INST0/RC_CGIC_INST CK )
;
- PCLKG
( PIN PCLKG ) ( RC_CG_HIER_INST4/RC_CGIC_INST CK )
( RC_CG_HIER_INST3/RC_CGIC_INST CK ) ( RC_CG_HIER_INST2/RC_CGIC_INST CK )
;
- PRESETn
( PIN PRESETn ) ( reg_curr_val_reg\[14\] RN ) ( reg_curr_val_reg\[16\] RN )
( reg_curr_val_reg\[27\] RN ) ( reg_curr_val_reg\[26\] RN )
( reg_curr_val_reg\[25\] RN ) ( reg_curr_val_reg\[24\] RN )
( reg_curr_val_reg\[20\] RN ) ( reg_curr_val_reg\[19\] RN )
( reg_curr_val_reg\[18\] RN ) ( reg_curr_val_reg\[17\] RN )
( reg_curr_val_reg\[15\] RN ) ( reg_curr_val_reg\[13\] RN )
( reg_reload_val_reg\[31\] RN ) ( reg_reload_val_reg\[30\] RN )
( reg_reload_val_reg\[27\] RN ) ( reg_reload_val_reg\[26\] RN )
( reg_reload_val_reg\[25\] RN ) ( reg_reload_val_reg\[24\] RN )
( reg_reload_val_reg\[23\] RN ) ( reg_reload_val_reg\[21\] RN )
( reg_reload_val_reg\[20\] RN ) ( reg_reload_val_reg\[19\] RN )
( reg_reload_val_reg\[18\] RN ) ( reg_reload_val_reg\[17\] RN )
( reg_reload_val_reg\[16\] RN ) ( reg_reload_val_reg\[15\] RN )
( reg_reload_val_reg\[14\] RN ) ( reg_reload_val_reg\[13\] RN )
( FE_OFC0_PRESETn A )
;
- PSEL
( PIN PSEL ) ( g4612__7675 B ) ( g4563__4296 C ) ( g4553__6083 AN )
;
- PADDR[11]
( PIN PADDR[11] ) ( g4760 D ) ( g4560__1857 D )
;
- PADDR[10]
( PIN PADDR[10] ) ( g4760 C ) ( g4560__1857 C )
;
- PADDR[9]
( PIN PADDR[9] ) ( g4760 B ) ( g4555__5795 B )
;
- PADDR[8]
( PIN PADDR[8] ) ( g4760 A ) ( g4555__5795 A )
;
- PADDR[7]
( PIN PADDR[7] ) ( g4759 D ) ( g4560__1857 B )
;
- PADDR[6]
( PIN PADDR[6] ) ( g4759 C ) ( g4560__1857 A )
;
- PADDR[5]
( PIN PADDR[5] ) ( g4759 B ) ( g4607__1309 B ) ( g4605__2683 B )
( g4552__2250 A0 ) ( g4532__1309 B )
;
- PADDR[4]
( PIN PADDR[4] ) ( g4759 A ) ( g4607__1309 A ) ( g4605__2683 AN )
( g4554__2703 A0 )
;
- PADDR[3]
( PIN PADDR[3] ) ( g4611__2391 A ) ( g4610__2900 A ) ( g4608__6877 B )
( g4552__2250 A1 ) ( g4547__5703 A ) ( g4428__2250 A0N ) ( g4425__5703 A0 )
;
- PADDR[2]
( PIN PADDR[2] ) ( g4614 A ) ( g4611__2391 B ) ( g4608__6877 A )
( g4557__1840 A ) ( g4532__1309 A ) ( g4435__1857 A0 )
;
- PENABLE
( PIN PENABLE ) ( g4563__4296 AN )
;
- PWRITE
( PIN PWRITE ) ( g4612__7675 AN ) ( g4563__4296 B )
;
- PWDATA[31]
( PIN PWDATA[31] ) ( g4678__7114 B0 ) ( reg_reload_val_reg\[31\] D )
;
- PWDATA[30]
( PIN PWDATA[30] ) ( g4677__5703 B0 ) ( reg_reload_val_reg\[30\] D )
;
- PWDATA[29]
( PIN PWDATA[29] ) ( g4676__5953 B0 ) ( reg_reload_val_reg\[29\] D )
;
- PWDATA[28]
( PIN PWDATA[28] ) ( g4675__1786 B0 ) ( reg_reload_val_reg\[28\] D )
;
- PWDATA[27]
( PIN PWDATA[27] ) ( g4674__8757 B0 ) ( reg_reload_val_reg\[27\] D )
;
- PWDATA[26]
( PIN PWDATA[26] ) ( g4673__7118 B0 ) ( reg_reload_val_reg\[26\] D )
;
- PWDATA[25]
( PIN PWDATA[25] ) ( g4672__7675 B0 ) ( reg_reload_val_reg\[25\] D )
;
- PWDATA[24]
( PIN PWDATA[24] ) ( g4671__2391 B0 ) ( reg_reload_val_reg\[24\] D )
;
- PWDATA[23]
( PIN PWDATA[23] ) ( g4670__2900 B0 ) ( reg_reload_val_reg\[23\] D )
;
- PWDATA[22]
( PIN PWDATA[22] ) ( g4669__6877 B0 ) ( reg_reload_val_reg\[22\] D )
;
- PWDATA[21]
( PIN PWDATA[21] ) ( g4642__9906 B0 ) ( reg_reload_val_reg\[21\] D )
;
- PWDATA[20]
( PIN PWDATA[20] ) ( g4657__2683 B0 ) ( reg_reload_val_reg\[20\] D )
;
- PWDATA[19]
( PIN PWDATA[19] ) ( g4656__9682 B0 ) ( reg_reload_val_reg\[19\] D )
;
- PWDATA[18]
( PIN PWDATA[18] ) ( g4655__4547 B0 ) ( reg_reload_val_reg\[18\] D )
;
- PWDATA[17]
( PIN PWDATA[17] ) ( g4646__1474 B0 ) ( reg_reload_val_reg\[17\] D )
;
- PWDATA[16]
( PIN PWDATA[16] ) ( g4645__3772 B0 ) ( reg_reload_val_reg\[16\] D )
;
- PWDATA[15]
( PIN PWDATA[15] ) ( g4644__4296 B0 ) ( reg_reload_val_reg\[15\] D )
;
- PWDATA[14]
( PIN PWDATA[14] ) ( g4643__8780 B0 ) ( reg_reload_val_reg\[14\] D )
;
- PWDATA[13]
( PIN PWDATA[13] ) ( g4617__5266 B0 ) ( reg_reload_val_reg\[13\] D )
;
- PWDATA[12]
( PIN PWDATA[12] ) ( g4616__7114 B0 ) ( reg_reload_val_reg\[12\] D )
;
- PWDATA[11]
( PIN PWDATA[11] ) ( g4658__1309 B0 ) ( reg_reload_val_reg\[11\] D )
;
- PWDATA[10]
( PIN PWDATA[10] ) ( g4615__5703 B0 ) ( reg_reload_val_reg\[10\] D )
;
- PWDATA[9]
( PIN PWDATA[9] ) ( g4653__1786 B0 ) ( reg_reload_val_reg\[9\] D )
;
- PWDATA[8]
( PIN PWDATA[8] ) ( g4626__6083 B0 ) ( reg_reload_val_reg\[8\] D )
;
- PWDATA[7]
( PIN PWDATA[7] ) ( g4631__5019 B0 ) ( reg_reload_val_reg\[7\] D )
;
- PWDATA[6]
( PIN PWDATA[6] ) ( g4630__1840 B0 ) ( reg_reload_val_reg\[6\] D )
;
- PWDATA[5]
( PIN PWDATA[5] ) ( g4629__7344 B0 ) ( reg_reload_val_reg\[5\] D )
;
- PWDATA[4]
( PIN PWDATA[4] ) ( g4628__5795 B0 ) ( reg_reload_val_reg\[4\] D )
;
- PWDATA[3]
( PIN PWDATA[3] ) ( reg_ctrl_reg\[3\] D ) ( g4627__2703 B0 )
( reg_reload_val_reg\[3\] D )
;
- PWDATA[2]
( PIN PWDATA[2] ) ( reg_ctrl_reg\[2\] D ) ( g4632__1857 B0 )
( reg_reload_val_reg\[2\] D )
;
- PWDATA[1]
( PIN PWDATA[1] ) ( g4618__2250 B0 ) ( reg_reload_val_reg\[1\] D )
( reg_ctrl_reg\[1\] D )
;
- PWDATA[0]
( PIN PWDATA[0] ) ( g4698 A ) ( g4654__5953 B0 ) ( reg_reload_val_reg\[0\] D )
( reg_ctrl_reg\[0\] D )
;
- ECOREVNUM[3]
( PIN ECOREVNUM[3] ) ( g4613 A )
;
- ECOREVNUM[2]
( PIN ECOREVNUM[2] ) ( g4492__9906 B0 )
;
- ECOREVNUM[1]
( PIN ECOREVNUM[1] ) ( g4431__5795 B0 )
;
- ECOREVNUM[0]
( PIN ECOREVNUM[0] ) ( g4430__2703 B0 )
;
- PRDATA[31]
( PIN PRDATA[31] ) ( FE_OFC174_PRDATA_31 Y )
;
- PRDATA[30]
( PIN PRDATA[30] ) ( FE_OFC144_PRDATA_30 Y )
;
- PRDATA[29]
( PIN PRDATA[29] ) ( FE_OFC136_PRDATA_29 Y )
;
- PRDATA[28]
( PIN PRDATA[28] ) ( FE_OFC146_PRDATA_28 Y )
;
- PRDATA[27]
( PIN PRDATA[27] ) ( FE_OFC74_PRDATA_27 Y )
;
- PRDATA[26]
( PIN PRDATA[26] ) ( FE_OFC138_PRDATA_26 Y )
;
- PRDATA[25]
( PIN PRDATA[25] ) ( FE_OFC182_PRDATA_25 Y )
;
- PRDATA[24]
( PIN PRDATA[24] ) ( FE_OFC148_PRDATA_24 Y )
;
- PRDATA[23]
( PIN PRDATA[23] ) ( FE_OFC76_PRDATA_23 Y )
;
- PRDATA[22]
( PIN PRDATA[22] ) ( FE_OFC176_PRDATA_22 Y )
;
- PRDATA[21]
( PIN PRDATA[21] ) ( FE_OFC156_PRDATA_21 Y )
;
- PRDATA[20]
( PIN PRDATA[20] ) ( FE_OFC82_PRDATA_20 Y )
;
- PRDATA[19]
( PIN PRDATA[19] ) ( FE_OFC168_PRDATA_19 Y )
;
- PRDATA[18]
( PIN PRDATA[18] ) ( FE_OFC158_PRDATA_18 Y )
;
- PRDATA[17]
( PIN PRDATA[17] ) ( FE_OFC80_PRDATA_17 Y )
;
- PRDATA[16]
( PIN PRDATA[16] ) ( FE_OFC150_PRDATA_16 Y )
;
- PRDATA[15]
( PIN PRDATA[15] ) ( FE_OFC152_PRDATA_15 Y )
;
- PRDATA[14]
( PIN PRDATA[14] ) ( FE_OFC140_PRDATA_14 Y )
;
- PRDATA[13]
( PIN PRDATA[13] ) ( FE_OFC160_PRDATA_13 Y )
;
- PRDATA[12]
( PIN PRDATA[12] ) ( FE_OFC86_PRDATA_12 Y )
;
- PRDATA[11]
( PIN PRDATA[11] ) ( FE_OFC142_PRDATA_11 Y )
;
- PRDATA[10]
( PIN PRDATA[10] ) ( FE_OFC84_PRDATA_10 Y )
;
- PRDATA[9]
( PIN PRDATA[9] ) ( FE_OFC162_PRDATA_9 Y )
;
- PRDATA[8]
( PIN PRDATA[8] ) ( FE_OFC172_PRDATA_8 Y )
;
- PRDATA[7]
( PIN PRDATA[7] ) ( FE_OFC154_PRDATA_7 Y )
;
- PRDATA[6]
( PIN PRDATA[6] ) ( FE_OFC170_PRDATA_6 Y )
;
- PRDATA[5]
( PIN PRDATA[5] ) ( FE_OFC178_PRDATA_5 Y )
;
- PRDATA[4]
( PIN PRDATA[4] ) ( FE_OFC164_PRDATA_4 Y )
;
- PRDATA[3]
( PIN PRDATA[3] ) ( FE_OFC166_PRDATA_3 Y )
;
- PRDATA[2]
( PIN PRDATA[2] ) ( FE_OFC180_PRDATA_2 Y )
;
- PRDATA[1]
( PIN PRDATA[1] ) ( FE_OFC72_PRDATA_1 Y )
;
- PRDATA[0]
( PIN PRDATA[0] ) ( FE_OFC78_PRDATA_0 Y )
;
- PREADY
( PIN PREADY )
;
- PSLVERR
( PIN PSLVERR )
;
- EXTIN
( PIN EXTIN ) ( ext_in_sync1_reg D )
;
- TIMERINT
( PIN TIMERINT ) ( FE_OFC70_TIMERINT Y )
;
- read_mux_byte0_reg[7]
( g4419__1786 AN ) ( read_mux_byte0_reg_reg\[7\] Q )
;
- read_mux_byte0_reg[6]
( g4418__8757 AN ) ( read_mux_byte0_reg_reg\[6\] Q )
;
- read_mux_byte0_reg[5]
( g4407__2683 AN ) ( read_mux_byte0_reg_reg\[5\] Q )
;
- read_mux_byte0_reg[4]
( g4406__9682 AN ) ( read_mux_byte0_reg_reg\[4\] Q )
;
- read_mux_byte0_reg[3]
( g4405__4547 AN ) ( read_mux_byte0_reg_reg\[3\] Q )
;
- read_mux_byte0_reg[2]
( g4417__7118 AN ) ( read_mux_byte0_reg_reg\[2\] Q )
;
- read_mux_byte0_reg[1]
( g4420__5953 AN ) ( read_mux_byte0_reg_reg\[1\] Q )
;
- read_mux_byte0_reg[0]
( g4408__1309 AN ) ( read_mux_byte0_reg_reg\[0\] Q )
;
- reg_ctrl[3]
( reg_ctrl_reg\[3\] Q ) ( g4520__9906 A0 )
;
- reg_ctrl[2]
( reg_ctrl_reg\[2\] Q ) ( g4556__7344 B )
;
- reg_ctrl[1]
( g4556__7344 A ) ( g4519__1857 A0 ) ( reg_ctrl_reg\[1\] Q )
;
- reg_ctrl[0]
( g4758 C0 ) ( g4434__5019 C0 ) ( reg_ctrl_reg\[0\] Q )
;
- reg_reload_val[31]
( g4742 A0 ) ( g4678__7114 A0 ) ( reg_reload_val_reg\[31\] Q )
;
- reg_reload_val[30]
( g4741 A0 ) ( g4677__5703 A0 ) ( reg_reload_val_reg\[30\] Q )
;
- reg_reload_val[29]
( g4739 A0 ) ( g4676__5953 A0 ) ( reg_reload_val_reg\[29\] Q )
;
- reg_reload_val[28]
( g4743 A0 ) ( g4675__1786 A0 ) ( reg_reload_val_reg\[28\] Q )
;
- reg_reload_val[27]
( g4746 A0 ) ( g4674__8757 A0 ) ( reg_reload_val_reg\[27\] Q )
;
- reg_reload_val[26]
( g4748 A0 ) ( g4673__7118 A0 ) ( reg_reload_val_reg\[26\] Q )
;
- reg_reload_val[25]
( g4752 A0 ) ( g4672__7675 A0 ) ( reg_reload_val_reg\[25\] Q )
;
- reg_reload_val[24]
( g4755 A0 ) ( g4671__2391 A0 ) ( reg_reload_val_reg\[24\] Q )
;
- reg_reload_val[23]
( g4735 A0 ) ( g4670__2900 A0 ) ( reg_reload_val_reg\[23\] Q )
;
- reg_reload_val[22]
( g4740 A0 ) ( g4669__6877 A0 ) ( reg_reload_val_reg\[22\] Q )
;
- reg_reload_val[21]
( g4734 A0 ) ( g4642__9906 A0 ) ( reg_reload_val_reg\[21\] Q )
;
- reg_reload_val[20]
( g4744 A0 ) ( g4657__2683 A0 ) ( reg_reload_val_reg\[20\] Q )
;
- reg_reload_val[19]
( g4745 A0 ) ( g4656__9682 A0 ) ( reg_reload_val_reg\[19\] Q )
;
- reg_reload_val[18]
( g4747 A0 ) ( g4655__4547 A0 ) ( reg_reload_val_reg\[18\] Q )
;
- reg_reload_val[17]
( g4749 A0 ) ( g4646__1474 A0 ) ( reg_reload_val_reg\[17\] Q )
;
- reg_reload_val[16]
( g4750 A0 ) ( g4645__3772 A0 ) ( reg_reload_val_reg\[16\] Q )
;
- reg_reload_val[15]
( g4751 A0 ) ( g4644__4296 A0 ) ( reg_reload_val_reg\[15\] Q )
;
- reg_reload_val[14]
( g4753 A0 ) ( g4643__8780 A0 ) ( reg_reload_val_reg\[14\] Q )
;
- reg_reload_val[13]
( g4754 A0 ) ( g4617__5266 C0 ) ( reg_reload_val_reg\[13\] Q )
;
- reg_reload_val[12]
( g4756 A0 ) ( g4616__7114 C0 ) ( reg_reload_val_reg\[12\] Q )
;
- reg_reload_val[11]
( g4757 A0 ) ( g4658__1309 A0 ) ( reg_reload_val_reg\[11\] Q )
;
- reg_reload_val[10]
( g4736 A0 ) ( g4615__5703 C0 ) ( reg_reload_val_reg\[10\] Q )
;
- reg_reload_val[9]
( g4737 A0 ) ( g4653__1786 C0 ) ( reg_reload_val_reg\[9\] Q )
;
- reg_reload_val[8]
( g4738 A0 ) ( g4626__6083 C0 ) ( reg_reload_val_reg\[8\] Q )
;
- reg_reload_val[7]
( g4631__5019 C0 ) ( g4522__4296 A ) ( reg_reload_val_reg\[7\] Q )
;
- reg_reload_val[6]
( g4630__1840 C0 ) ( g4492__9906 A0 ) ( reg_reload_val_reg\[6\] Q )
;
- reg_reload_val[5]
( g4629__7344 C0 ) ( g4431__5795 A0 ) ( reg_reload_val_reg\[5\] Q )
;
- reg_reload_val[4]
( g4628__5795 C0 ) ( g4430__2703 A0 ) ( reg_reload_val_reg\[4\] Q )
;
- reg_reload_val[3]
( g4627__2703 C0 ) ( g4520__9906 B0 ) ( reg_reload_val_reg\[3\] Q )
;
- reg_reload_val[2]
( g4632__1857 C0 ) ( g4524__1474 A ) ( reg_reload_val_reg\[2\] Q )
;
- reg_reload_val[1]
( g4618__2250 C0 ) ( g4519__1857 B0 ) ( reg_reload_val_reg\[1\] Q )
;
- reg_reload_val[0]
( g4654__5953 C0 ) ( g4427__5266 A0N ) ( reg_reload_val_reg\[0\] Q )
;
- reg_curr_val[31]
( dec_sub_195_45_g1644__4296 A ) ( g4690__9906 A )
( reg_curr_val_reg\[31\] Q ) ( reg_curr_val_reg\[31\] D ) ( g4474__2900 AN )
;
- reg_curr_val[30]
( dec_sub_195_45_g1663__5266 C ) ( dec_sub_195_45_g1620__1309 A0 )
( g4690__9906 B ) ( reg_curr_val_reg\[30\] Q ) ( reg_curr_val_reg\[30\] D )
( g4464__9906 AN )
;
- reg_curr_val[29]
( dec_sub_195_45_g1663__5266 B ) ( dec_sub_195_45_g1635__2703 AN )
( dec_sub_195_45_g1632__2250 A ) ( g4692__4296 A )
( reg_curr_val_reg\[29\] Q ) ( reg_curr_val_reg\[29\] D ) ( g4479__1786 AN )
;
- reg_curr_val[28]
( dec_sub_195_45_g1663__5266 A ) ( dec_sub_195_45_g1657__7118 A )
( dec_sub_195_45_g1649__9682 A0 ) ( g4692__4296 B )
( reg_curr_val_reg\[28\] Q ) ( reg_curr_val_reg\[28\] D ) ( g4489__1840 AN )
;
- reg_curr_val[27]
( dec_sub_195_45_g1688__8757 C ) ( dec_sub_195_45_g1630__7114 B0 )
( g4689__1857 A ) ( reg_curr_val_reg\[27\] Q ) ( reg_curr_val_reg\[27\] D )
( g4503__2391 AN )
;
- reg_curr_val[26]
( dec_sub_195_45_g1688__8757 D ) ( dec_sub_195_45_g1642__9906 A )
( dec_sub_195_45_g1630__7114 A0 ) ( g4689__1857 B )
( reg_curr_val_reg\[26\] Q ) ( reg_curr_val_reg\[26\] D ) ( g4505__7118 AN )
;
- reg_curr_val[25]
( dec_sub_195_45_g1696__6083 A ) ( dec_sub_195_45_g1636__5795 B )
( g4690__9906 D ) ( reg_curr_val_reg\[25\] Q ) ( reg_curr_val_reg\[25\] D )
( g4509__5703 AN )
;
- reg_curr_val[24]
( dec_sub_195_45_g1696__6083 B ) ( dec_sub_195_45_g1662__7114 A )
( dec_sub_195_45_g1652__6877 A0 ) ( g4690__9906 C )
( reg_curr_val_reg\[24\] Q ) ( reg_curr_val_reg\[24\] D ) ( g4517__1840 AN )
;
- reg_curr_val[23]
( dec_sub_195_45_g1698__5795 A ) ( dec_sub_195_45_g1631__5266 B0 )
( g4691__8780 A ) ( reg_curr_val_reg\[23\] Q ) ( reg_curr_val_reg\[23\] D )
( g4469__4547 AN )
;
- reg_curr_val[22]
( dec_sub_195_45_g1698__5795 B ) ( dec_sub_195_45_g1643__8780 A )
( dec_sub_195_45_g1631__5266 A0 ) ( g4691__8780 D )
( reg_curr_val_reg\[22\] Q ) ( reg_curr_val_reg\[22\] D ) ( g4476__7675 AN )
;
- reg_curr_val[21]
( dec_sub_195_45_g1699__7344 A ) ( dec_sub_195_45_g1629__5703 A0N )
( g4691__8780 C ) ( reg_curr_val_reg\[21\] Q ) ( reg_curr_val_reg\[21\] D )
( g4481__5703 AN )
;
- reg_curr_val[20]
( dec_sub_195_45_g1699__7344 B ) ( dec_sub_195_45_g1655__2391 A )
( dec_sub_195_45_g1650__2683 A0N ) ( g4689__1857 C )
( reg_curr_val_reg\[20\] Q ) ( reg_curr_val_reg\[20\] D ) ( g4485__6083 AN )
;
- reg_curr_val[19]
( dec_sub_195_45_g1700__1840 A ) ( dec_sub_195_45_g1628__5953 A0N )
( g4696__9682 D ) ( reg_curr_val_reg\[19\] Q ) ( reg_curr_val_reg\[19\] D )
( g4462__5019 AN )
;
- reg_curr_val[18]
( dec_sub_195_45_g1700__1840 B ) ( dec_sub_195_45_g1661__5703 A )
( dec_sub_195_45_g1651__1309 A0N ) ( g4696__9682 C )
( reg_curr_val_reg\[18\] Q ) ( reg_curr_val_reg\[18\] D ) ( g4495__3772 AN )
;
- reg_curr_val[17]
( dec_sub_195_45_g1702__1857 A ) ( dec_sub_195_45_g1639__5019 B )
( g4696__9682 B ) ( reg_curr_val_reg\[17\] Q ) ( reg_curr_val_reg\[17\] D )
( g4499__2683 AN )
;
- reg_curr_val[16]
( reg_curr_val_reg\[16\] Q ) ( reg_curr_val_reg\[16\] D )
( dec_sub_195_45_g1702__1857 B ) ( g4696__9682 A ) ( g4502__2900 AN )
;
- reg_curr_val[15]
( dec_sub_195_45_g1695__2250 A ) ( dec_sub_195_45_g1647__1474 B )
( g4694__1474 D ) ( reg_curr_val_reg\[15\] Q ) ( reg_curr_val_reg\[15\] D )
( g4507__1786 AN )
;
- reg_curr_val[14]
( reg_curr_val_reg\[14\] Q ) ( reg_curr_val_reg\[14\] D )
( dec_sub_195_45_g1695__2250 B ) ( g4694__1474 C ) ( g4510__7114 AN )
;
- reg_curr_val[13]
( dec_sub_195_45_g1678__4547 B ) ( dec_sub_195_45_g1659__1786 B )
( g4694__1474 B ) ( reg_curr_val_reg\[13\] Q ) ( reg_curr_val_reg\[13\] D )
( g4512__2250 AN )
;
- reg_curr_val[12]
( dec_sub_195_45_g1678__4547 A ) ( dec_sub_195_45_g1676__3772 A )
( dec_sub_195_45_g1674__8780 A0 ) ( g4694__1474 A )
( reg_curr_val_reg\[12\] Q ) ( reg_curr_val_reg\[12\] D ) ( g4514__2703 AN )
;
- reg_curr_val[11]
( dec_sub_195_45_g1692__7114 B ) ( dec_sub_195_45_g1624__7675 B )
( g4693__3772 D ) ( reg_curr_val_reg\[11\] Q ) ( reg_curr_val_reg\[11\] D )
( g4491__1857 AN )
;
- reg_curr_val[10]
( dec_sub_195_45_g1692__7114 C ) ( dec_sub_195_45_g1640__1857 A )
( dec_sub_195_45_g1638__1840 A0 ) ( g4693__3772 C )
( reg_curr_val_reg\[10\] Q ) ( reg_curr_val_reg\[10\] D ) ( g4466__4296 AN )
;
- reg_curr_val[9]
( dec_sub_195_45_g1692__7114 A ) ( dec_sub_195_45_g1666__2703 A )
( dec_sub_195_45_g1660__5953 A0N ) ( g4693__3772 B )
( reg_curr_val_reg\[9\] Q ) ( reg_curr_val_reg\[9\] D ) ( g4470__9682 AN )
;
- reg_curr_val[8]
( dec_sub_195_45_g1692__7114 D ) ( dec_sub_195_45_g1681__2683 A )
( dec_sub_195_45_g1677__1474 A0N ) ( g4693__3772 A )
( reg_curr_val_reg\[8\] Q ) ( reg_curr_val_reg\[8\] D ) ( g4473__6877 AN )
;
- reg_curr_val[7]
( g4761 D ) ( dec_sub_195_45_g1626__8757 B ) ( g4695__4547 D )
( reg_curr_val_reg\[7\] Q ) ( reg_curr_val_reg\[7\] D ) ( g4477__7118 AN )
;
- reg_curr_val[6]
( g4761 B ) ( reg_curr_val_reg\[6\] Q ) ( reg_curr_val_reg\[6\] D )
( g4695__4547 C ) ( g4480__5953 AN )
;
- reg_curr_val[5]
( g4761 C ) ( dec_sub_195_45_g1670__5019 A ) ( dec_sub_195_45_g1668__7344 A0 )
( g4695__4547 B ) ( reg_curr_val_reg\[5\] Q ) ( reg_curr_val_reg\[5\] D )
( g4482__7114 AN )
;
- reg_curr_val[4]
( g4761 A ) ( dec_sub_195_45_g1686__7675 AN ) ( dec_sub_195_45_g1685__2391 B )
( g4695__4547 A ) ( reg_curr_val_reg\[4\] Q ) ( reg_curr_val_reg\[4\] D )
( g4483__5266 AN )
;
- reg_curr_val[3]
( dec_sub_195_45_g1701__5019 A ) ( dec_sub_195_45_g1675__4296 B )
( g4691__8780 B ) ( reg_curr_val_reg\[3\] Q ) ( reg_curr_val_reg\[3\] D )
( g4488__7344 AN )
;
- reg_curr_val[2]
( reg_curr_val_reg\[2\] Q ) ( reg_curr_val_reg\[2\] D )
( dec_sub_195_45_g1701__5019 B ) ( g4692__4296 D ) ( g4490__5019 AN )
;
- reg_curr_val[1]
( dec_sub_195_45_g1697__2703 A ) ( dec_sub_195_45_g1691__5703 A1 )
( g4692__4296 C ) ( reg_curr_val_reg\[1\] Q ) ( reg_curr_val_reg\[1\] D )
( g4518__5019 AN )
;
- reg_curr_val[0]
( reg_curr_val_reg\[0\] Q ) ( reg_curr_val_reg\[0\] D )
( dec_sub_195_45_g1697__2703 B ) ( dec_sub_195_45_g1691__5703 A0 )
( g4697__2683 B ) ( g4494__4296 AN )
;
- UNCONNECTED
( ext_in_delay_reg Q )
;
- dec_sub_195_45_n_548
( dec_sub_195_45_g1624__7675 Y ) ( dec_sub_195_45_g1621__6877 B )
;
- dec_sub_195_45_n_550
( dec_sub_195_45_g1626__8757 Y ) ( dec_sub_195_45_g1625__7118 B )
;
- dec_sub_195_45_n_554
( dec_sub_195_45_g1630__7114 Y ) ( dec_sub_195_45_g1622__2900 B )
;
- dec_sub_195_45_n_556
( dec_sub_195_45_g1631__5266 Y ) ( dec_sub_195_45_g1623__2391 B )
;
- dec_sub_195_45_n_560
( dec_sub_195_45_g1634__6083 S ) ( dec_sub_195_45_g1633 A )
;
- dec_sub_195_45_n_561
( dec_sub_195_45_g1634__6083 CO ) ( dec_sub_195_45_g1626__8757 AN )
;
- dec_sub_195_45_n_562
( dec_sub_195_45_g1635__2703 Y ) ( dec_sub_195_45_g1620__1309 A1 )
;
- dec_sub_195_45_n_565
( dec_sub_195_45_g1636__5795 Y ) ( dec_sub_195_45_g1627__1786 B )
;
- dec_sub_195_45_n_570
( dec_sub_195_45_g1639__5019 Y ) ( dec_sub_195_45_g1637__7344 B )
;
- dec_sub_195_45_n_571
( dec_sub_195_45_g1640__1857 Y ) ( dec_sub_195_45_g1638__1840 B0 )
( dec_sub_195_45_g1624__7675 AN )
;
- dec_sub_195_45_n_582
( dec_sub_195_45_g1646__3772 S ) ( dec_sub_195_45_g1645 A )
;
- dec_sub_195_45_n_583
( dec_sub_195_45_g1646__3772 CO ) ( dec_sub_195_45_g1639__5019 AN )
;
- dec_sub_195_45_n_585
( dec_sub_195_45_g2__9906 B ) ( dec_sub_195_45_g1647__1474 Y )
;
- dec_sub_195_45_n_599
( dec_sub_195_45_g1655__2391 Y ) ( dec_sub_195_45_g1650__2683 B0 )
( dec_sub_195_45_g1629__5703 A1N )
;
- dec_sub_195_45_n_600
( dec_sub_195_45_g1656__7675 Y ) ( dec_sub_195_45_g1642__9906 B )
( dec_sub_195_45_g1630__7114 A1 ) ( dec_sub_195_45_g1627__1786 A )
;
- dec_sub_195_45_n_601
( dec_sub_195_45_g1657__7118 Y ) ( dec_sub_195_45_g1649__9682 B0 )
( dec_sub_195_45_g1635__2703 B ) ( dec_sub_195_45_g1632__2250 B )
;
- dec_sub_195_45_n_602
( dec_sub_195_45_g1658__8757 Y ) ( dec_sub_195_45_g1643__8780 B )
( dec_sub_195_45_g1631__5266 A1 ) ( dec_sub_195_45_g1629__5703 B0 )
;
- dec_sub_195_45_n_603
( dec_sub_195_45_g1654__2900 S ) ( dec_sub_195_45_g1653 A )
;
- dec_sub_195_45_n_604
( dec_sub_195_45_g1654__2900 CO ) ( dec_sub_195_45_g1647__1474 AN )
;
- dec_sub_195_45_n_608
( dec_sub_195_45_g1661__5703 Y ) ( dec_sub_195_45_g1651__1309 B0 )
( dec_sub_195_45_g1628__5953 A1N )
;
- dec_sub_195_45_n_609
( dec_sub_195_45_g1662__7114 Y ) ( dec_sub_195_45_g1652__6877 B0 )
( dec_sub_195_45_g1636__5795 AN )
;
- dec_sub_195_45_n_610
( dec_sub_195_45_g1663__5266 Y ) ( dec_sub_195_45_g1644__4296 B )
( dec_sub_195_45_g1620__1309 B0 )
;
- dec_sub_195_45_n_611
( dec_sub_195_45_g1659__1786 Y ) ( dec_sub_195_45_g1648__4547 B )
;
- dec_sub_195_45_n_616
( dec_sub_195_45_g1664__2250 Y ) ( dec_sub_195_45_g1658__8757 AN )
( dec_sub_195_45_g1655__2391 B ) ( dec_sub_195_45_g1650__2683 A1N )
( dec_sub_195_45_g1628__5953 B0 )
;
- dec_sub_195_45_n_618
( dec_sub_195_45_g1665__6083 Y ) ( dec_sub_195_45_g1661__5703 B )
( dec_sub_195_45_g1651__1309 A1N ) ( dec_sub_195_45_g1637__7344 A )
;
- dec_sub_195_45_n_619
( dec_sub_195_45_g1666__2703 Y ) ( dec_sub_195_45_g1660__5953 B0 )
( dec_sub_195_45_g1640__1857 B ) ( dec_sub_195_45_g1638__1840 A1 )
;
- dec_sub_195_45_n_622
( dec_sub_195_45_g1667__5795 Y ) ( dec_sub_195_45_g1662__7114 B )
( dec_sub_195_45_g1656__7675 AN ) ( dec_sub_195_45_g1652__6877 A1 )
( dec_sub_195_45_g1623__2391 A )
;
- dec_sub_195_45_n_625
( dec_sub_195_45_g1669__1840 Y ) ( dec_sub_195_45_g1663__5266 D )
( dec_sub_195_45_g1657__7118 B ) ( dec_sub_195_45_g1649__9682 A1 )
( dec_sub_195_45_g1622__2900 A )
;
- dec_sub_195_45_n_627
( dec_sub_195_45_g1670__5019 Y ) ( dec_sub_195_45_g1668__7344 B0 )
( dec_sub_195_45_g1634__6083 B )
;
- dec_sub_195_45_n_631
( dec_sub_195_45_g2__9906 AN ) ( dec_sub_195_45_g1673__9906 Y )
( dec_sub_195_45_g1669__1840 B ) ( dec_sub_195_45_g1667__5795 B )
( dec_sub_195_45_g1665__6083 B ) ( dec_sub_195_45_g1664__2250 B )
( dec_sub_195_45_g1646__3772 B )
;
- dec_sub_195_45_n_637
( dec_sub_195_45_g1675__4296 Y ) ( dec_sub_195_45_g1671__1857 B )
;
- dec_sub_195_45_n_638
( dec_sub_195_45_g1676__3772 Y ) ( dec_sub_195_45_g1674__8780 B0 )
( dec_sub_195_45_g1659__1786 AN )
;
- dec_sub_195_45_n_642
( dec_sub_195_45_g1678__4547 Y ) ( dec_sub_195_45_g1673__9906 B )
( dec_sub_195_45_g1654__2900 B ) ( dec_sub_195_45_g1648__4547 AN )
;
- dec_sub_195_45_n_645
( dec_sub_195_45_g1680__9682 S ) ( dec_sub_195_45_g1679 A )
;
- dec_sub_195_45_n_646
( dec_sub_195_45_g1680__9682 CO ) ( dec_sub_195_45_g1675__4296 AN )
;
- dec_sub_195_45_n_647
( dec_sub_195_45_g1681__2683 Y ) ( dec_sub_195_45_g1677__1474 B0 )
( dec_sub_195_45_g1666__2703 B ) ( dec_sub_195_45_g1660__5953 A1N )
;
- dec_sub_195_45_n_649
( dec_sub_195_45_g1682__1309 Y ) ( dec_sub_195_45_g1678__4547 C )
( dec_sub_195_45_g1676__3772 B ) ( dec_sub_195_45_g1674__8780 A1 )
( dec_sub_195_45_g1621__6877 A )
;
- dec_sub_195_45_n_651
( dec_sub_195_45_g1684__2900 Y ) ( dec_sub_195_45_g1682__1309 B )
( dec_sub_195_45_g1681__2683 B ) ( dec_sub_195_45_g1677__1474 A1N )
( dec_sub_195_45_g1625__7118 A )
;
- dec_sub_195_45_n_653
( dec_sub_195_45_g1685__2391 Y ) ( dec_sub_195_45_g1683__6877 A )
;
- dec_sub_195_45_n_654
( dec_sub_195_45_g1686__7675 Y ) ( dec_sub_195_45_g1683__6877 B )
( dec_sub_195_45_g1670__5019 B ) ( dec_sub_195_45_g1668__7344 A1 )
;
- dec_sub_195_45_n_656
( dec_sub_195_45_g1687__7118 Y ) ( dec_sub_195_45_g1686__7675 B )
( dec_sub_195_45_g1685__2391 AN ) ( dec_sub_195_45_g1684__2900 B )
( dec_sub_195_45_g1671__1857 AN )
;
- dec_sub_195_45_n_658
( dec_sub_195_45_g1688__8757 Y ) ( dec_sub_195_45_g1669__1840 A )
;
- dec_sub_195_45_n_663
( dec_sub_195_45_g1689__1786 Y ) ( dec_sub_195_45_g1688__8757 BN )
( dec_sub_195_45_g1667__5795 A )
;
- dec_sub_195_45_n_666
( dec_sub_195_45_g1690__5953 Y ) ( dec_sub_195_45_g1689__1786 C )
( dec_sub_195_45_g1664__2250 A )
;
- dec_sub_195_45_n_669
( dec_sub_195_45_g1692__7114 Y ) ( dec_sub_195_45_g1682__1309 A )
;
- dec_sub_195_45_n_673
( dec_sub_195_45_g1695__2250 Y ) ( dec_sub_195_45_g1673__9906 A )
;
- dec_sub_195_45_n_675
( dec_sub_195_45_g1696__6083 Y ) ( dec_sub_195_45_g1688__8757 AN )
( dec_sub_195_45_g1656__7675 B )
;
- dec_sub_195_45_n_677
( dec_sub_195_45_g1697__2703 Y ) ( dec_sub_195_45_g1691__5703 B0 )
( dec_sub_195_45_g1687__7118 B ) ( dec_sub_195_45_g1680__9682 B )
;
- dec_sub_195_45_n_680
( dec_sub_195_45_g1698__5795 Y ) ( dec_sub_195_45_g1689__1786 A )
;
- dec_sub_195_45_n_682
( dec_sub_195_45_g1699__7344 Y ) ( dec_sub_195_45_g1689__1786 B )
( dec_sub_195_45_g1658__8757 B )
;
- dec_sub_195_45_n_684
( dec_sub_195_45_g1700__1840 Y ) ( dec_sub_195_45_g1690__5953 A )
;
- dec_sub_195_45_n_686
( dec_sub_195_45_g1701__5019 Y ) ( dec_sub_195_45_g1687__7118 A )
;
- dec_sub_195_45_n_688
( dec_sub_195_45_g1702__1857 Y ) ( dec_sub_195_45_g1690__5953 B )
( dec_sub_195_45_g1665__6083 A )
;
- dec_sub_195_45_n_698
( reg_curr_val_reg\[6\] QN ) ( dec_sub_195_45_g1634__6083 A )
;
- dec_sub_195_45_n_701
( reg_curr_val_reg\[16\] QN ) ( dec_sub_195_45_g1646__3772 A )
;
- dec_sub_195_45_n_715
( reg_curr_val_reg\[14\] QN ) ( dec_sub_195_45_g1654__2900 A )
;
- dec_sub_195_45_n_721
( reg_curr_val_reg\[2\] QN ) ( dec_sub_195_45_g1680__9682 A )
;
- ext_in_delay
( g4758 B0 ) ( ext_in_delay_reg QN )
;
- ext_in_enable
( g4553__6083 Y ) ( RC_CG_HIER_INST1/RC_CGIC_INST E )
;
- ext_in_sync1
( ext_in_sync2_reg D ) ( ext_in_sync1_reg Q )
;
- ext_in_sync2
( g4758 A0 ) ( ext_in_sync2_reg Q ) ( ext_in_delay_reg D )
;
- n_0
( g4683__5795 C ) ( g4680__2250 A ) ( g4545__1786 Y ) ( g4444__1309 B )
( g3185 A )
;
- n_1
( reg_curr_val_reg\[0\] QN ) ( g4685__7344 C ) ( g4654__5953 A0 )
;
- n_2
( g4698 Y ) ( g4681__6083 A0 )
;
- n_3
( g4697__2683 Y ) ( g4683__5795 A )
;
- n_4
( g4696__9682 Y ) ( g4688__5019 B )
;
- n_5
( g4695__4547 Y ) ( g4688__5019 A )
;
- n_6
( g4694__1474 Y ) ( g4688__5019 C )
;
- n_7
( g4693__3772 Y ) ( g4688__5019 D )
;
- n_8
( g4692__4296 Y ) ( g4687__1840 B )
;
- n_9
( g4691__8780 Y ) ( g4687__1840 A )
;
- n_10
( g4690__9906 Y ) ( g4689__1857 D )
;
- n_11
( g4689__1857 Y ) ( g4687__1840 C )
;
- n_12
( g4688__5019 Y ) ( g4687__1840 D )
;
- n_13
( g4686 Y ) ( g4683__5795 B )
;
- n_14
( g2 AN ) ( g4687__1840 Y ) ( g4686 A ) ( g4685__7344 D )
;
- n_15
( g4685__7344 Y ) ( g4684 A ) ( g4681__6083 B0 )
;
- n_16
( g4684 Y ) ( g4679__5266 B )
;
- n_18
( g4683__5795 Y ) ( g4678__7114 A1 ) ( g4677__5703 A1 ) ( g4676__5953 A1 )
( g4675__1786 A1 ) ( g4674__8757 A1 ) ( g4673__7118 A1 ) ( g4672__7675 A1 )
( g4671__2391 A1 ) ( g4670__2900 A1 ) ( g4669__6877 A1 ) ( g4658__1309 A1 )
( g4657__2683 A1 ) ( g4656__9682 A1 ) ( g4655__4547 A1 ) ( g4646__1474 A1 )
( g4645__3772 A1 ) ( g4644__4296 A1 ) ( g4643__8780 A1 ) ( g4642__9906 A1 )
( g4632__1857 C1 ) ( g4631__5019 C1 ) ( g4630__1840 C1 ) ( g4629__7344 C1 )
( g4628__5795 C1 ) ( g4627__2703 C1 ) ( g4626__6083 C1 ) ( g4618__2250 C1 )
( g4617__5266 C1 ) ( g4616__7114 C1 ) ( g4615__5703 C1 ) ( g4654__5953 C1 )
( g4653__1786 C1 )
;
- n_19
( g4681__6083 Y ) ( g4679__5266 S0 )
;
- n_20
( g4680__2250 Y ) ( g4678__7114 C0 ) ( g4677__5703 C0 ) ( g4676__5953 C0 )
( g4675__1786 C0 ) ( g4674__8757 C0 ) ( g4673__7118 C0 ) ( g4672__7675 C0 )
( g4671__2391 C0 ) ( g4670__2900 C0 ) ( g4669__6877 C0 ) ( g4658__1309 C1 )
( g4657__2683 C0 ) ( g4656__9682 C0 ) ( g4655__4547 C0 ) ( g4646__1474 C0 )
( g4645__3772 C1 ) ( g4644__4296 C0 ) ( g4643__8780 C0 ) ( g4642__9906 C0 )
( g4632__1857 A1 ) ( g4631__5019 A1 ) ( g4630__1840 A1 ) ( g4629__7344 A1 )
( g4628__5795 A1 ) ( g4627__2703 A1 ) ( g4626__6083 A1 ) ( g4618__2250 A1 )
( g4617__5266 A0 ) ( g4616__7114 A1 ) ( g4615__5703 A0 ) ( g4654__5953 A1 )
( g4653__1786 A1 )
;
- n_21
( g4679__5266 Y ) ( reg_timer_int_reg D )
;
- n_22
( g4678__7114 Y ) ( g4668 A )
;
- n_23
( g4677__5703 Y ) ( g4667 A )
;
- n_24
( g4676__5953 Y ) ( g4666 A )
;
- n_25
( g4675__1786 Y ) ( g4665 A )
;
- n_26
( g4674__8757 Y ) ( g4664 A )
;
- n_27
( g4673__7118 Y ) ( g4663 A )
;
- n_28
( g4672__7675 Y ) ( g4662 A )
;
- n_29
( g4671__2391 Y ) ( g4661 A )
;
- n_30
( g4670__2900 Y ) ( g4660 A )
;
- n_31
( g4669__6877 Y ) ( g4659 A )
;
- n_32
( g4668 Y ) ( reg_curr_val_reg\[31\] SI )
;
- n_33
( g4667 Y ) ( reg_curr_val_reg\[30\] SI )
;
- n_34
( g4666 Y ) ( reg_curr_val_reg\[29\] SI )
;
- n_35
( g4665 Y ) ( reg_curr_val_reg\[28\] SI )
;
- n_36
( g4664 Y ) ( reg_curr_val_reg\[27\] SI )
;
- n_37
( g4663 Y ) ( reg_curr_val_reg\[26\] SI )
;
- n_38
( g4662 Y ) ( reg_curr_val_reg\[25\] SI )
;
- n_39
( g4661 Y ) ( reg_curr_val_reg\[24\] SI )
;
- n_40
( g4660 Y ) ( reg_curr_val_reg\[23\] SI )
;
- n_41
( g4659 Y ) ( reg_curr_val_reg\[22\] SI )
;
- n_42
( g4658__1309 Y ) ( g4641 A )
;
- n_43
( g4657__2683 Y ) ( g4640 A )
;
- n_44
( g4656__9682 Y ) ( g4639 A )
;
- n_45
( g4655__4547 Y ) ( g4638 A )
;
- n_46
( g4646__1474 Y ) ( g4637 A )
;
- n_47
( g4645__3772 Y ) ( g4636 A )
;
- n_48
( g4644__4296 Y ) ( g4635 A )
;
- n_49
( g4643__8780 Y ) ( g4634 A )
;
- n_50
( g4642__9906 Y ) ( g4633 A )
;
- n_51
( g4641 Y ) ( reg_curr_val_reg\[11\] SI )
;
- n_52
( g4640 Y ) ( reg_curr_val_reg\[20\] SI )
;
- n_53
( g4639 Y ) ( reg_curr_val_reg\[19\] SI )
;
- n_54
( g4638 Y ) ( reg_curr_val_reg\[18\] SI )
;
- n_55
( g4637 Y ) ( reg_curr_val_reg\[17\] SI )
;
- n_56
( reg_curr_val_reg\[16\] SI ) ( g4636 Y )
;
- n_57
( g4635 Y ) ( reg_curr_val_reg\[15\] SI )
;
- n_58
( reg_curr_val_reg\[14\] SI ) ( g4634 Y )
;
- n_59
( g4633 Y ) ( reg_curr_val_reg\[21\] SI )
;
- n_60
( g4632__1857 Y ) ( g4625 A )
;
- n_61
( g4631__5019 Y ) ( g4624 A )
;
- n_62
( g4630__1840 Y ) ( g4623 A )
;
- n_63
( g4629__7344 Y ) ( g4622 A )
;
- n_64
( g4628__5795 Y ) ( g4621 A )
;
- n_65
( g4627__2703 Y ) ( g4620 A )
;
- n_66
( g4626__6083 Y ) ( g4619 A )
;
- n_67
( reg_curr_val_reg\[2\] SI ) ( g4625 Y )
;
- n_68
( g4624 Y ) ( reg_curr_val_reg\[7\] SI )
;
- n_69
( reg_curr_val_reg\[6\] SI ) ( g4623 Y )
;
- n_70
( g4622 Y ) ( reg_curr_val_reg\[5\] SI )
;
- n_71
( g4621 Y ) ( reg_curr_val_reg\[4\] SI )
;
- n_72
( g4620 Y ) ( reg_curr_val_reg\[3\] SI )
;
- n_73
( g4619 Y ) ( reg_curr_val_reg\[8\] SI )
;
- n_74
( g4618__2250 Y ) ( g4652 A )
;
- n_75
( g4617__5266 Y ) ( g4651 A )
;
- n_76
( g4616__7114 Y ) ( g4650 A )
;
- n_77
( g4615__5703 Y ) ( g4609 A )
;
- n_78
( g4654__5953 Y ) ( g4649 A )
;
- n_79
( g4653__1786 Y ) ( g4648 A )
;
- n_80
( g4652 Y ) ( reg_curr_val_reg\[1\] SI )
;
- n_81
( g4651 Y ) ( reg_curr_val_reg\[13\] SI )
;
- n_82
( g4650 Y ) ( reg_curr_val_reg\[12\] SI )
;
- n_83
( g4609 Y ) ( reg_curr_val_reg\[10\] SI )
;
- n_84
( reg_curr_val_reg\[0\] SI ) ( g4649 Y )
;
- n_85
( g4648 Y ) ( reg_curr_val_reg\[9\] SI )
;
- n_87
( g2__7118 Y ) ( g4518__5019 B ) ( g4517__1840 B ) ( g4514__2703 B )
( g4512__2250 B ) ( g4510__7114 B ) ( g4509__5703 B ) ( g4507__1786 B )
( g4505__7118 B ) ( g4503__2391 B ) ( g4502__2900 B ) ( g4499__2683 B )
( g4495__3772 B ) ( g4494__4296 B ) ( g4491__1857 B ) ( g4490__5019 B )
( g4489__1840 B ) ( g4488__7344 B ) ( g4485__6083 B ) ( g4483__5266 B )
( g4482__7114 B ) ( g4481__5703 B ) ( g4480__5953 B ) ( g4479__1786 B )
( g4477__7118 B ) ( g4476__7675 B ) ( g4474__2900 B ) ( g4473__6877 B )
( g4470__9682 B ) ( g4469__4547 B ) ( g4466__4296 B ) ( g4464__9906 B )
( g4462__5019 B )
;
- n_88
( g4614 Y ) ( g4610__2900 B ) ( g4547__5703 B )
;
- n_89
( g4613 Y ) ( g4432__7344 A0 )
;
- n_94
( g2__7118 AN ) ( g4612__7675 Y ) ( g4588 A )
;
- n_95
( g4611__2391 Y ) ( g4554__2703 A1 ) ( g4539__7675 B ) ( g4461__1840 S0 )
;
- n_96
( g4610__2900 Y ) ( g4545__1786 A ) ( g4544__8757 A ) ( g4433__1840 A0 )
;
- n_97
( g4608__6877 Y ) ( g4559__5019 A ) ( g4538__2391 A )
;
- n_98
( g4607__1309 Y ) ( g4557__1840 B ) ( g4531__2683 AN )
;
- n_99
( g4605__2683 Y ) ( g4559__5019 B ) ( g4533__6877 A )
;
- n_100
( g4758 B1 ) ( reg_ctrl_reg\[2\] QN ) ( g4436__9906 B0 )
;
- n_101
( g4560__1857 Y ) ( g4555__5795 C )
;
- n_104
( g4559__5019 Y ) ( g4546__5953 B ) ( g4540__7118 A )
;
- n_105
( g4557__1840 Y ) ( g4554__2703 B0 ) ( g4552__2250 B0 )
;
- n_106
( g4758 A1 ) ( g4556__7344 Y ) ( g4553__6083 B )
;
- n_107
( g4554__2703 Y ) ( g4436__9906 A0 )
;
- n_108
( g4552__2250 Y ) ( g4434__5019 A0 )
;
- n_109
( g4555__5795 Y ) ( g4546__5953 AN ) ( g4540__7118 B )
;
- n_111
( g4551__5266 Y ) ( g4548 A ) ( g4547__5703 C )
;
- n_112
( g4548 Y ) ( g4544__8757 B ) ( g4539__7675 AN ) ( g4538__2391 B )
;
- n_113
( g4647__8757 AN ) ( g4547__5703 Y ) ( g4534__2900 B ) ( g4524__1474 B )
( g4522__4296 B ) ( g4520__9906 B1 ) ( g4519__1857 B1 ) ( g4492__9906 A1 )
( g4431__5795 A1 ) ( g4430__2703 A1 ) ( g4427__5266 A1N )
;
- n_114
( g4546__5953 Y ) ( g4542 A ) ( g4432__7344 A1 )
;
- n_115
( g4542 Y ) ( g4492__9906 B1 ) ( g4431__5795 B1 ) ( g4430__2703 B1 )
;
- n_116
( g2__7118 B ) ( g4544__8757 Y ) ( g4525__4547 AN )
;
- n_117
( g4537 Y ) ( g4533__6877 B ) ( g4436__9906 A1 )
;
- n_118
( g4540__7118 Y ) ( g4537 A ) ( g4532__1309 C ) ( g4531__2683 B )
( g4434__5019 A1 )
;
- n_119
( g4536 Y ) ( g4520__9906 A1 ) ( g4519__1857 A1 ) ( g4434__5019 C1 )
;
- n_120
( g4539__7675 Y ) ( g4536 A ) ( g4523__3772 B ) ( g4436__9906 B1 )
;
- n_121
( g4538__2391 Y ) ( g4535 A ) ( g4434__5019 B1 )
;
- n_123
( g4757 A1 ) ( g4756 A1 ) ( g4755 A1 ) ( g4754 A1 ) ( g4753 A1 ) ( g4752 A1 )
( g4751 A1 ) ( g4750 A1 ) ( g4749 A1 ) ( g4748 A1 ) ( g4747 A1 ) ( g4746 A1 )
( g4745 A1 ) ( g4744 A1 ) ( g4743 A1 ) ( g4742 A1 ) ( g4741 A1 ) ( g4740 A1 )
( g4739 A1 ) ( g4738 A1 ) ( g4737 A1 ) ( g4736 A1 ) ( g4735 A1 ) ( g4734 A1 )
( g4534__2900 Y )
;
- n_124
( g4533__6877 Y ) ( g4528 A ) ( g4428__2250 A1N )
;
- n_125
( g4528 Y ) ( g4461__1840 A ) ( g4435__1857 A1 ) ( g4425__5703 A1 )
;
- n_126
( g4532__1309 Y ) ( g4527 A ) ( g4432__7344 C0 )
;
- n_127
( g4527 Y ) ( g4431__5795 C0 ) ( g4430__2703 C0 )
;
- n_128
( g4531__2683 Y ) ( g4461__1840 B ) ( g4433__1840 A1 )
;
- n_129
( g4524__1474 Y ) ( g4436__9906 C0 )
;
- n_130
( g4522__4296 Y ) ( g4432__7344 B0 )
;
- n_131
( g4525__4547 Y ) ( g4420__5953 B ) ( g4419__1786 B ) ( g4418__8757 B )
( g4417__7118 B ) ( g4408__1309 B ) ( g4407__2683 B ) ( g4406__9682 B )
( g4405__4547 B )
;
- n_132
( g4520__9906 Y ) ( g4426__7114 A )
;
- n_133
( g4519__1857 Y ) ( g4435__1857 B0 )
;
- n_134
( g4518__5019 Y ) ( g4412__7675 B )
;
- n_135
( g4755 B0 ) ( g4517__1840 Y )
;
- n_138
( g4756 B0 ) ( g4514__2703 Y )
;
- n_140
( g4754 B0 ) ( g4512__2250 Y )
;
- n_142
( g4753 B0 ) ( g4510__7114 Y )
;
- n_143
( g4752 B0 ) ( g4509__5703 Y )
;
- n_145
( g4751 B0 ) ( g4507__1786 Y )
;
- n_147
( g4748 B0 ) ( g4505__7118 Y )
;
- n_149
( g4746 B0 ) ( g4503__2391 Y )
;
- n_150
( g4750 B0 ) ( g4502__2900 Y )
;
- n_153
( g4749 B0 ) ( g4499__2683 Y )
;
- n_157
( g4747 B0 ) ( g4495__3772 Y )
;
- n_158
( g4494__4296 Y ) ( g4404__1474 B )
;
- n_160
( g4492__9906 Y ) ( g4433__1840 B0 )
;
- n_161
( g4757 B0 ) ( g4491__1857 Y )
;
- n_162
( g4490__5019 Y ) ( g4409__6877 B )
;
- n_163
( g4743 B0 ) ( g4489__1840 Y )
;
- n_164
( g4488__7344 Y ) ( g4403__3772 B )
;
- n_167
( g4744 B0 ) ( g4485__6083 Y )
;
- n_169
( g4483__5266 Y ) ( g4402__4296 B )
;
- n_170
( g4482__7114 Y ) ( g4401__8780 B )
;
- n_171
( g4734 B0 ) ( g4481__5703 Y )
;
- n_172
( g4480__5953 Y ) ( g4411__2391 B )
;
- n_173
( g4739 B0 ) ( g4479__1786 Y )
;
- n_175
( g4477__7118 Y ) ( g4410__2900 B )
;
- n_176
( g4740 B0 ) ( g4476__7675 Y )
;
- n_178
( g4742 B0 ) ( g4474__2900 Y )
;
- n_179
( g4738 B0 ) ( g4473__6877 Y )
;
- n_182
( g4737 B0 ) ( g4470__9682 Y )
;
- n_183
( g4735 B0 ) ( g4469__4547 Y )
;
- n_186
( g4736 B0 ) ( g4466__4296 Y )
;
- n_188
( g4741 B0 ) ( g4464__9906 Y )
;
- n_190
( g4745 B0 ) ( g4462__5019 Y )
;
- n_191
( g4461__1840 Y ) ( g4426__7114 B )
;
- n_215
( g4436__9906 Y ) ( read_mux_byte0_reg_reg\[2\] D )
;
- n_216
( g4435__1857 Y ) ( read_mux_byte0_reg_reg\[1\] D )
;
- n_217
( g4434__5019 Y ) ( g4427__5266 B0 )
;
- n_218
( g4433__1840 Y ) ( read_mux_byte0_reg_reg\[6\] D )
;
- n_219
( g4432__7344 Y ) ( read_mux_byte0_reg_reg\[7\] D )
;
- n_220
( g4431__5795 Y ) ( g4425__5703 B0 )
;
- n_221
( g4430__2703 Y ) ( g4428__2250 B0 )
;
- n_223
( g4428__2250 Y ) ( read_mux_byte0_reg_reg\[4\] D )
;
- n_224
( g4427__5266 Y ) ( read_mux_byte0_reg_reg\[0\] D )
;
- n_225
( g4426__7114 Y ) ( read_mux_byte0_reg_reg\[3\] D )
;
- n_226
( g4425__5703 Y ) ( read_mux_byte0_reg_reg\[5\] D )
;
- n_227
( g4420__5953 Y ) ( g4412__7675 A )
;
- n_228
( g4419__1786 Y ) ( g4410__2900 A )
;
- n_229
( g4418__8757 Y ) ( g4411__2391 A )
;
- n_230
( g4417__7118 Y ) ( g4409__6877 A )
;
- n_235
( g4408__1309 Y ) ( g4404__1474 A )
;
- n_236
( g4407__2683 Y ) ( g4401__8780 A )
;
- n_237
( g4406__9682 Y ) ( g4402__4296 A )
;
- n_238
( g4405__4547 Y ) ( g4403__3772 A )
;
- n_243
( g4678__7114 B1 ) ( g4677__5703 B1 ) ( g4676__5953 B1 ) ( g4675__1786 B1 )
( g4674__8757 B1 ) ( g4673__7118 B1 ) ( g4672__7675 B1 ) ( g4671__2391 B1 )
( g4670__2900 B1 ) ( g4669__6877 B1 ) ( g4658__1309 B1 ) ( g4657__2683 B1 )
( g4656__9682 B1 ) ( g4655__4547 B1 ) ( g4646__1474 B1 ) ( g4645__3772 B1 )
( g4644__4296 B1 ) ( g4643__8780 B1 ) ( g4642__9906 B1 ) ( g4632__1857 B1 )
( g4631__5019 B1 ) ( g4630__1840 B1 ) ( g4629__7344 B1 ) ( g4628__5795 B1 )
( g4627__2703 B1 ) ( g4626__6083 B1 ) ( g4618__2250 B1 ) ( g4617__5266 B1 )
( g4616__7114 B1 ) ( g4615__5703 B1 ) ( g4654__5953 B1 ) ( g4653__1786 B1 )
( g3185 Y )
;
- n_244
( reg_ctrl_reg\[3\] QN ) ( g4685__7344 A )
;
- n_247
( g4681__6083 A2 ) ( g4535 Y )
;
- n_250
( g4681__6083 A1 ) ( g4647__8757 B ) ( g4563__4296 Y ) ( g4545__1786 B )
( g4523__3772 A )
;
- n_251
( dec_sub_195_45_g1691__5703 Y ) ( g4618__2250 A0 )
;
- n_252
( dec_sub_195_45_g1679 Y ) ( g4632__1857 A0 )
;
- n_253
( dec_sub_195_45_g1671__1857 Y ) ( g4627__2703 A0 )
;
- n_254
( dec_sub_195_45_g1683__6877 Y ) ( g4628__5795 A0 )
;
- n_255
( dec_sub_195_45_g1668__7344 Y ) ( g4629__7344 A0 )
;
- n_256
( dec_sub_195_45_g1633 Y ) ( g4630__1840 A0 )
;
- n_257
( dec_sub_195_45_g1625__7118 Y ) ( g4631__5019 A0 )
;
- n_258
( dec_sub_195_45_g1677__1474 Y ) ( g4626__6083 A0 )
;
- n_259
( dec_sub_195_45_g1660__5953 Y ) ( g4653__1786 A0 )
;
- n_260
( dec_sub_195_45_g1638__1840 Y ) ( g4615__5703 A1 )
;
- n_261
( dec_sub_195_45_g1621__6877 Y ) ( g4658__1309 C0 )
;
- n_262
( dec_sub_195_45_g1674__8780 Y ) ( g4616__7114 A0 )
;
- n_263
( dec_sub_195_45_g1648__4547 Y ) ( g4617__5266 A1 )
;
- n_264
( dec_sub_195_45_g1653 Y ) ( g4643__8780 C1 )
;
- n_265
( dec_sub_195_45_g2__9906 Y ) ( g4644__4296 C1 )
;
- n_266
( dec_sub_195_45_g1645 Y ) ( g4645__3772 C0 )
;
- n_267
( dec_sub_195_45_g1637__7344 Y ) ( g4646__1474 C1 )
;
- n_268
( dec_sub_195_45_g1651__1309 Y ) ( g4655__4547 C1 )
;
- n_269
( dec_sub_195_45_g1628__5953 Y ) ( g4656__9682 C1 )
;
- n_270
( dec_sub_195_45_g1650__2683 Y ) ( g4657__2683 C1 )
;
- n_271
( dec_sub_195_45_g1629__5703 Y ) ( g4642__9906 C1 )
;
- n_272
( dec_sub_195_45_g1643__8780 Y ) ( g4669__6877 C1 )
;
- n_273
( dec_sub_195_45_g1623__2391 Y ) ( g4670__2900 C1 )
;
- n_274
( dec_sub_195_45_g1652__6877 Y ) ( g4671__2391 C1 )
;
- n_275
( dec_sub_195_45_g1627__1786 Y ) ( g4672__7675 C1 )
;
- n_276
( dec_sub_195_45_g1642__9906 Y ) ( g4673__7118 C1 )
;
- n_277
( dec_sub_195_45_g1622__2900 Y ) ( g4674__8757 C1 )
;
- n_278
( dec_sub_195_45_g1649__9682 Y ) ( g4675__1786 C1 )
;
- n_279
( dec_sub_195_45_g1632__2250 Y ) ( g4676__5953 C1 )
;
- n_280
( dec_sub_195_45_g1620__1309 Y ) ( g4677__5703 C1 )
;
- n_281
( dec_sub_195_45_g1644__4296 Y ) ( g4678__7114 C1 )
;
- n_362
( reg_curr_val_reg\[2\] SE ) ( reg_curr_val_reg\[14\] SE )
( reg_curr_val_reg\[16\] SE ) ( reg_curr_val_reg\[6\] SE )
( reg_curr_val_reg\[0\] SE ) ( reg_curr_val_reg\[31\] SE )
( reg_curr_val_reg\[30\] SE ) ( reg_curr_val_reg\[29\] SE )
( reg_curr_val_reg\[28\] SE ) ( reg_curr_val_reg\[27\] SE )
( reg_curr_val_reg\[26\] SE ) ( reg_curr_val_reg\[25\] SE )
( reg_curr_val_reg\[24\] SE ) ( reg_curr_val_reg\[23\] SE )
( reg_curr_val_reg\[22\] SE ) ( reg_curr_val_reg\[21\] SE )
( reg_curr_val_reg\[20\] SE ) ( reg_curr_val_reg\[19\] SE )
( reg_curr_val_reg\[18\] SE ) ( reg_curr_val_reg\[17\] SE )
( reg_curr_val_reg\[15\] SE ) ( reg_curr_val_reg\[13\] SE )
( reg_curr_val_reg\[12\] SE ) ( reg_curr_val_reg\[11\] SE )
( reg_curr_val_reg\[10\] SE ) ( reg_curr_val_reg\[9\] SE )
( reg_curr_val_reg\[8\] SE ) ( reg_curr_val_reg\[7\] SE )
( reg_curr_val_reg\[5\] SE ) ( reg_curr_val_reg\[4\] SE )
( reg_curr_val_reg\[3\] SE ) ( reg_curr_val_reg\[1\] SE ) ( g4444__1309 Y )
( RC_CG_HIER_INST0/RC_CGIC_INST E )
;
- n_368
( g2 Y ) ( g4680__2250 B )
;
- n_393
( g4758 Y ) ( g2 B ) ( g4697__2683 A ) ( g4685__7344 B ) ( g4444__1309 A )
;
- n_394
( g4759 Y ) ( g4551__5266 B ) ( g4545__1786 D )
;
- n_395
( g4760 Y ) ( g4551__5266 A ) ( g4545__1786 C )
;
- n_396
( g4761 Y ) ( dec_sub_195_45_g1684__2900 A )
;
- rc_gclk
( reg_curr_val_reg\[2\] CK ) ( reg_curr_val_reg\[14\] CK )
( reg_curr_val_reg\[16\] CK ) ( reg_curr_val_reg\[6\] CK )
( reg_curr_val_reg\[0\] CK ) ( reg_curr_val_reg\[31\] CK )
( reg_curr_val_reg\[30\] CK ) ( reg_curr_val_reg\[29\] CK )
( reg_curr_val_reg\[28\] CK ) ( reg_curr_val_reg\[27\] CK )
( reg_curr_val_reg\[26\] CK ) ( reg_curr_val_reg\[25\] CK )
( reg_curr_val_reg\[24\] CK ) ( reg_curr_val_reg\[23\] CK )
( reg_curr_val_reg\[22\] CK ) ( reg_curr_val_reg\[21\] CK )
( reg_curr_val_reg\[20\] CK ) ( reg_curr_val_reg\[19\] CK )
( reg_curr_val_reg\[18\] CK ) ( reg_curr_val_reg\[17\] CK )
( reg_curr_val_reg\[15\] CK ) ( reg_curr_val_reg\[13\] CK )
( reg_curr_val_reg\[12\] CK ) ( reg_curr_val_reg\[11\] CK )
( reg_curr_val_reg\[10\] CK ) ( reg_curr_val_reg\[9\] CK )
( reg_curr_val_reg\[8\] CK ) ( reg_curr_val_reg\[7\] CK )
( reg_curr_val_reg\[5\] CK ) ( reg_curr_val_reg\[4\] CK )
( reg_curr_val_reg\[3\] CK ) ( reg_curr_val_reg\[1\] CK )
( RC_CG_HIER_INST0/RC_CGIC_INST ECK )
;
- rc_gclk_2322
( ext_in_sync2_reg CK ) ( ext_in_sync1_reg CK ) ( ext_in_delay_reg CK )
( RC_CG_HIER_INST1/RC_CGIC_INST ECK )
;
- rc_gclk_2324
( reg_reload_val_reg\[31\] CK ) ( reg_reload_val_reg\[30\] CK )
( reg_reload_val_reg\[29\] CK ) ( reg_reload_val_reg\[28\] CK )
( reg_reload_val_reg\[27\] CK ) ( reg_reload_val_reg\[26\] CK )
( reg_reload_val_reg\[25\] CK ) ( reg_reload_val_reg\[24\] CK )
( reg_reload_val_reg\[23\] CK ) ( reg_reload_val_reg\[22\] CK )
( reg_reload_val_reg\[21\] CK ) ( reg_reload_val_reg\[20\] CK )
( reg_reload_val_reg\[19\] CK ) ( reg_reload_val_reg\[18\] CK )
( reg_reload_val_reg\[17\] CK ) ( reg_reload_val_reg\[16\] CK )
( reg_reload_val_reg\[15\] CK ) ( reg_reload_val_reg\[14\] CK )
( reg_reload_val_reg\[13\] CK ) ( reg_reload_val_reg\[12\] CK )
( reg_reload_val_reg\[11\] CK ) ( reg_reload_val_reg\[10\] CK )
( reg_reload_val_reg\[9\] CK ) ( reg_reload_val_reg\[8\] CK )
( reg_reload_val_reg\[7\] CK ) ( reg_reload_val_reg\[6\] CK )
( reg_reload_val_reg\[5\] CK ) ( reg_reload_val_reg\[4\] CK )
( reg_reload_val_reg\[3\] CK ) ( reg_reload_val_reg\[2\] CK )
( reg_reload_val_reg\[1\] CK ) ( reg_reload_val_reg\[0\] CK )
( RC_CG_HIER_INST2/RC_CGIC_INST ECK )
;
- rc_gclk_2326
( read_mux_byte0_reg_reg\[7\] CK ) ( read_mux_byte0_reg_reg\[6\] CK )
( read_mux_byte0_reg_reg\[5\] CK ) ( read_mux_byte0_reg_reg\[4\] CK )
( read_mux_byte0_reg_reg\[3\] CK ) ( read_mux_byte0_reg_reg\[2\] CK )
( read_mux_byte0_reg_reg\[1\] CK ) ( read_mux_byte0_reg_reg\[0\] CK )
( RC_CG_HIER_INST3/RC_CGIC_INST ECK )
;
- rc_gclk_2328
( reg_ctrl_reg\[2\] CK ) ( reg_ctrl_reg\[3\] CK ) ( reg_ctrl_reg\[1\] CK )
( reg_ctrl_reg\[0\] CK ) ( RC_CG_HIER_INST4/RC_CGIC_INST ECK )
;
- read_enable
( g4588 Y ) ( g4534__2900 A ) ( g4525__4547 B )
( RC_CG_HIER_INST3/RC_CGIC_INST E )
;
- write_enable00
( g4523__3772 Y ) ( RC_CG_HIER_INST4/RC_CGIC_INST E )
;
- write_enable08
( g4647__8757 Y ) ( RC_CG_HIER_INST2/RC_CGIC_INST E )
;
- RC_CG_HIER_INST0/test
( RC_CG_HIER_INST0/RC_CGIC_INST SE )
;
- RC_CG_HIER_INST1/test
( RC_CG_HIER_INST1/RC_CGIC_INST SE )
;
- RC_CG_HIER_INST2/test
( RC_CG_HIER_INST2/RC_CGIC_INST SE )
;
- RC_CG_HIER_INST3/test
( RC_CG_HIER_INST3/RC_CGIC_INST SE )
;
- RC_CG_HIER_INST4/test
( RC_CG_HIER_INST4/RC_CGIC_INST SE )
;
END NETS
END DESIGN
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