CELL LEF Example

 MACRO INVX1

  CLASS CORE ;

  FOREIGN INVX1 0 0 ;

  ORIGIN 0 0 ;

  SIZE 1.32 BY 5.04 ;

  SYMMETRY X Y ;

  SITE tsm3site ;

  LEQ INVXL ;

  PIN Y

  DIRECTION OUTPUT ;

  ANTENNADIFFAREA 0.7845 ;

  ANTENNAPARTIALMETALAREA 0.6868 LAYER Metal1 ;

  ANTENNAPARTIALMETALSIDEAREA 2.7454 LAYER Metal1 ;

     PORT

      LAYER Metal1 ;

      RECT 1.065 2.37 1.18 3.56 ;

      RECT 0.835 1.35 1.065 3.56 ;

      RECT 0.8 2.37 0.835 3.56 ;

     END

  END Y

  PIN A

  DIRECTION INPUT ;

  ANTENNAGATEAREA 0.27 ;

  ANTENNAPARTIALMETALAREA 0.2429 LAYER Metal1 ;

  ANTENNAPARTIALMETALSIDEAREA 1.0547 LAYER Metal1 ;

     PORT

      LAYER Metal1 ;

      RECT 0.14 1.82 0.57 2.385 ;

     END

  END A

  PIN VSS

  DIRECTION INOUT ;

  USE GROUND ;

  SHAPE ABUTMENT ;

     PORT

      LAYER Metal1 ;

      RECT 0.52 -0.4 1.32 0.4 ;

      RECT 0.18 -0.4 0.52 0.575 ;

      RECT 0 -0.4 0.18 0.4 ;

     END

  END VSS

  PIN VDD

  DIRECTION INOUT ;

  USE POWER ;

  SHAPE ABUTMENT ;

     PORT

      LAYER Metal1 ;

      RECT 0.52 4.64 1.32 5.44 ;

      RECT 0.18 4.465 0.52 5.44 ;

      RECT 0 4.64 0.18 5.44 ;

     END

  END VDD

END INVX1

 

Sample run.tcl to perform synthesis:

set DESIGN cmsdk_apb_uart

set_db / .init_lib_search_path {/home/cad/FOUNDRY/digital/45nm/LIBS/lib/max}

set_db / .init_hdl_search_path {/root/Desktop/apb_uart/rtl}

set_db / .library "slow.lib"

read_hdl "cmsdk_apb_uart.v"

elaborate $DESIGN

check_design -unresolved

read_sdc "/root/Desktop/apb_uart/sdc/apb_uart_sdc.sdc"

report_timing -lint

syn_generic

syn_map

syn_opt

write_hdl > outputs/output_gln.v

write_sdc > outputs/outsdc.sdc

 

Explanation

Let me break it down step by step:

---

1. Set Design Name:

set DESIGN cmsdk_apb_uart

• Assigns the name cmsdk_apb_uart to the variable DESIGN, which likely represents the module or design being worked on.

---

2. Library Search Paths:

set_db / .init_lib_search_path {/home/cad/FOUNDRY/digital/45nm/LIBS/lib/max}

set_db / .init_hdl_search_path {/root/Desktop/apb_uart/rtl}

• Specifies paths for searching libraries:
• .init_lib_search_path: Points to the directory containing the technology libraries (e.g., max folder for the 45nm process node).
• .init_hdl_search_path: Points to the directory containing the HDL (Hardware Description Language) files, such as Verilog.

---

3. Library Reference:

set_db / .library "slow.lib"

• Loads the timing library (slow.lib) required for synthesis and analysis. This file contains delay and power information for standard cells in the design.

---

4. Read HDL File:

read_hdl "cmsdk_apb_uart.v"

• Reads the Verilog file cmsdk_apb_uart.v into the tool. This file contains the module definition and hardware description.

---

5. Elaborate Design:

elaborate $DESIGN

• Elaborates the design specified by $DESIGN, resolving its hierarchy and preparing it for analysis or synthesis.

---

6. Check Design:

check_design -unresolved

• Performs a check for unresolved references or missing modules in the design. It ensures that all signals, modules, and entities are defined correctly.

---

7. Read SDC File:

read_sdc "/root/Desktop/apb_uart/sdc/apb_uart_sdc.sdc"

• Reads the Synopsys Design Constraints (SDC) file, which contains timing constraints for the design (e.g., clock definitions, timing paths, input/output delays).

---

8. Report Timing:

report_timing -lint

• Generates a timing report, possibly with linting, to identify issues related to timing paths, constraints, and violations.

---

9. Synthesis Steps:

syn_generic

syn_map

syn_opt

• syn_generic: Performs technology-independent synthesis, converting RTL into generic gates.
• syn_map: Maps the generic design onto technology-specific standard cells.
• syn_opt: Optimizes the mapped design for timing, area, and power.

---

10. Output Files:

write_hdl > outputs/output_gln.v

write_sdc > outputs/outsdc.sdc

• write_hdl: Writes the synthesized design as a Verilog file (output_gln.v).
• write_sdc: Writes the updated SDC file (outsdc.sdc), capturing new timing constraints after synthesis.

---

If you're running this workflow, ensure that the paths and libraries are correctly configured for your specific setup. Let me know if you'd like detailed guidance on any step!